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A new lock detector for Gardner's timing recovery method

IEEE transactions on consumer electronics, 2008-05, Vol.54 (2), p.349-352

2008

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1.1-V, 8-bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-to-digital converter in 0.18 μm CMOS with separated capacitor arrays

IET circuits, devices & systems, 2013-01, Vol.7 (1), p.1-8

2013

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Hybrid carrier recovery, blind equalization for high-order QAM signal constellations

IEEE transactions on consumer electronics, 2008-05, Vol.54 (2), p.333-335

2008

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An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs

IEEE transactions on circuits and systems. II, Express briefs, 2010-12, Vol.57 (12), p.961-965

2010

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A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion

IEEE transactions on circuits and systems. II, Express briefs, 2010-11, Vol.57 (11), p.853-857

2010

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A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

Analog integrated circuits and signal processing, 2013-11, Vol.77 (2), p.285-289

2013

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A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over −80-dB IM3

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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A DC-offset cancellation circuit for PGA in baseband communication

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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An 8.38 fJ/conversion-step 0.6 V 8-b 4.35 MS/s asynchronous SAR ADC in 65 nm CMOS

Analog integrated circuits and signal processing, 2012-10, Vol.73 (1), p.265-272

2012

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1.1-V, 8-bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-to-digital converter in 0.18 [mu]m CMOS with separated capacitor arrays

IET circuits, devices & systems, 2013-01, Vol.7 (1), p.1

2013

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A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

Journal of circuits, systems, and computers, 2013-04, Vol.22 (4), p.1350017

2013

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A 5-bit 125-MS/s 367-µW ADC in 65-nm CMOS

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012, p.1-4

2012

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A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS

Journal of circuits, systems, and computers, 2013-04, Vol.22 (4), p.1350027

2013

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A fast bootstrapped switch for high-speed high-resolution A/D converter

2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010, p.382-385

2010

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Clock gating -A power optimization technique for smart card

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014, p.1-3

2014

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A 0.8-V 48μW 82dB SNDR 10-kHz bandwidth ΣΔ modulator

2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2012, p.89-91

2012

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A ΣΔ modulator for low power energy meter application

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012, p.1-3

2012

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A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique

Microelectronics, 2012-12, Vol.43 (12), p.941-948

2012

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A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2012, p.80-82

2012

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A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS

2011 9th IEEE International Conference on ASIC, 2011, p.986-989

2011

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A modified background calibration technique for multi-bit delta-sigma modulators

2011 3rd International Conference on Advanced Computer Control, 2011, p.206-208

2011

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Design and realization of large dynamic range low pass filter with wide tuneable cut-off bandwidth

2009 9th International Conference on Electronic Measurement & Instruments, 2009, p.2-563-2-566

2009

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A 22mW 10-bit 150-MS/s pipelined ADC in 1.2V 65nm CMOS

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, p.454-456

2010

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A 15fJ/conversion-step 8-bit 50MS/s asynchronous SAR ADC with efficient charge recycling technique

Microelectronics, 2012-12, Vol.43 (12), p.941-948

2012

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A new lock detector for Gardner's timing recovery method

1.1-V, 8-bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-to-digital converter in 0.18 μm CMOS with separated capacitor arrays

Hybrid carrier recovery, blind equalization for high-order QAM signal constellations

An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs

A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion

A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over −80-dB IM3

A DC-offset cancellation circuit for PGA in baseband communication

An 8.38 fJ/conversion-step 0.6 V 8-b 4.35 MS/s asynchronous SAR ADC in 65 nm CMOS

1.1-V, 8-bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-to-digital converter in 0.18 [mu]m CMOS with separated capacitor arrays

A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

A 5-bit 125-MS/s 367-µW ADC in 65-nm CMOS

A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS

A fast bootstrapped switch for high-speed high-resolution A/D converter

Clock gating -A power optimization technique for smart card

A 0.8-V 48μW 82dB SNDR 10-kHz bandwidth ΣΔ modulator

A ΣΔ modulator for low power energy meter application

A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique

A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS

A modified background calibration technique for multi-bit delta-sigma modulators

Design and realization of large dynamic range low pass filter with wide tuneable cut-off bandwidth

A 22mW 10-bit 150-MS/s pipelined ADC in 1.2V 65nm CMOS

A 15fJ/conversion-step 8-bit 50MS/s asynchronous SAR ADC with efficient charge recycling technique

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