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Asymptotic Probability Extraction for Nonnormal Performance Distributions

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-01, Vol.26 (1), p.16-37

2007

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Inductance 101: modeling and extraction

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.323-328

2001

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PRIMA: passive reduced-order interconnect macromodeling algorithm

IEEE transactions on computer-aided design of integrated circuits and systems, 1998-08, Vol.17 (8), p.645-654

1998

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Robust Analog/RF Circuit Design With Projection-Based Performance Modeling

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-01, Vol.26 (1), p.2-15

2007

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Modeling magnetic coupling for on-chip interconnect

Proceedings - ACM IEEE Design Automation Conference, 2001, p.335-340

2001

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Compact reduced-order modeling of weakly nonlinear analog and RF circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-02, Vol.24 (2), p.184-203

2005

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Min/max on-chip inductance models and delay metrics

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.341-346

2001

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High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T186-T187

2015

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Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-03, Vol.18 (3), p.293-300

1999

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Error bounds for capacitance extraction via window techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-03, Vol.18 (3), p.311-321

1999

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Efficient per-nonlinearity distortion analysis for analog and RF circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-10, Vol.22 (10), p.1297-1309

2003

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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

Proceedings of the IEEE, 2008-02, Vol.96 (2), p.343-365

2008

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The Elmore delay as a bound for RC trees with generalized input signals

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-01, Vol.16 (1), p.95-104

1997

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Metal-mask configurable RF front-end circuits

IEEE journal of solid-state circuits, 2004-08, Vol.39 (8), p.1347-1351

2004

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Asymptotic probability extraction for non-normal distributions of circuit performance

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.2-9

2004

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Efficient full-chip thermal modeling and analysis

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.319-326

2004

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Performance computation for precharacterized CMOS gates with RC loads

IEEE transactions on computer-aided design of integrated circuits and systems, 1996-05, Vol.15 (5), p.544-553

1996

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TETA: transistor-level waveform evaluation for timing analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-05, Vol.21 (5), p.605-616

2002

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On-chip induction modeling: basics and advanced methods

IEEE transactions on very large scale integration (VLSI) systems, 2002-12, Vol.10 (6), p.712-729

2002

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Parasitics extraction with multipole refinement

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-02, Vol.23 (2), p.288-292

2004

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IC thermal simulation and modeling via efficient multigrid-based approaches

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-09, Vol.25 (9), p.1763-1776

2006

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Global and local congestion optimization in technology mapping

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-04, Vol.22 (4), p.498-505

2003

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False coupling interactions in static timing analysis

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.726-731

2001

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Efficient harmonic balance simulation using multi-level frequency decomposition

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.677-682

2004

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Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-05, Vol.28 (5), p.623-637

2009

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Asymptotic Probability Extraction for Nonnormal Performance Distributions

Inductance 101: modeling and extraction

PRIMA: passive reduced-order interconnect macromodeling algorithm

Robust Analog/RF Circuit Design With Projection-Based Performance Modeling

Modeling magnetic coupling for on-chip interconnect

Compact reduced-order modeling of weakly nonlinear analog and RF circuits

Min/max on-chip inductance models and delay metrics

High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications

Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees

Error bounds for capacitance extraction via window techniques

Efficient per-nonlinearity distortion analysis for analog and RF circuits

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

The Elmore delay as a bound for RC trees with generalized input signals

Metal-mask configurable RF front-end circuits

Asymptotic probability extraction for non-normal distributions of circuit performance

Efficient full-chip thermal modeling and analysis

Performance computation for precharacterized CMOS gates with RC loads

TETA: transistor-level waveform evaluation for timing analysis

On-chip induction modeling: basics and advanced methods

Parasitics extraction with multipole refinement

IC thermal simulation and modeling via efficient multigrid-based approaches

Global and local congestion optimization in technology mapping

False coupling interactions in static timing analysis

Efficient harmonic balance simulation using multi-level frequency decomposition

Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty

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