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Electrical properties of heavily doped polycrystalline silicon-germanium films

IEEE transactions on electron devices, 1994-02, Vol.41 (2), p.228-232

1994

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Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

IEEE transactions on electron devices, 1994, Vol.41 (1), p.56-62

1994

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Anomalous co-diffusion effects of germanium on group III and V dopants in silicon

Applied physics letters, 1988-02, Vol.52 (6), p.471-473

1988

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PMOS transistors in LPCVD polycrystalline silicon-germanium films

IEEE electron device letters, 1991-11, Vol.12 (11), p.584-586

1991

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A self-aligned elevated source/drain MOSFET

IEEE electron device letters, 1990-09, Vol.11 (9), p.365-367

1990

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Low-temperature annealing of arsenic/phosphorus junctions

IEEE transactions on electron devices, 1991-02, Vol.38 (2), p.278-284

1991

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An ultra-shallow buried-channel PMOST using boron penetration

IEEE transactions on electron devices, 1993-01, Vol.40 (1), p.207-213

1993

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LDD MOSFETs using disposable sidewall spacer technology

IEEE electron device letters, 1988-04, Vol.9 (4), p.189-192

Pfiester, J.R.

1988

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Gain-enhanced LDD NMOS device using cesium implantation

IEEE transactions on electron devices, 1992-06, Vol.39 (6), p.1469-1476

1992

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Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

IEEE electron device letters, 1989-04, Vol.10 (4), p.147-149

Pfiester, J.R.

1989

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The influence of tilted source-drain implants on high-field effects in submicrometer MOSFETs

IEEE transactions on electron devices, 1988-12, Vol.35 (12), p.2119-2124

1988

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A new technique for forming a shallow link base in a double polysilicon bipolar transistor

IEEE transactions on electron devices, 1994-01, Vol.41 (1), p.63-68

1994

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Improved CMOS field isolation using germanium/boron implantation

IEEE electron device letters, 1988-08, Vol.9 (8), p.391-393

1988

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A novel CMOS VLSI isolation technology using selective chlorine implantation

IEEE electron device letters, 1988-11, Vol.9 (11), p.561-563

1988

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Poly-gate sidewall oxidation induced submicrometer MOSFET degradation

IEEE electron device letters, 1989-08, Vol.10 (8), p.367-369

1989

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A cobalt salicide CMOS process with TiN-strapped polysilicon gates

IEEE electron device letters, 1991-06, Vol.12 (6), p.350-352

1991

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Improved MOSFET short-channel device using germanium implantation

IEEE electron device letters, 1988-07, Vol.9 (7), p.343-346

1988

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Disposable polysilicon LDD spacer technology

IEEE transactions on electron devices, 1991-01, Vol.38 (1), p.39-46

1991

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An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

IEEE transactions on electron devices, 1991-11, Vol.38 (11), p.2460-2464

1991

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A novel PMOS SOI polysilicon transistor

IEEE electron device letters, 1990-08, Vol.11 (8), p.349-351

1990

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Performance limits of CMOS ULSI

IEEE transactions on electron devices, 1985-02, Vol.32 (2), p.333-343

1985

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A high-performance half-micrometer generation CMOS technology for fast SRAMs

IEEE transactions on electron devices, 1991-04, Vol.38 (4), p.876-886

1991

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An advanced 0.5- mu m CMOS disposable TiN LDD/salicide spacer process

IEEE electron device letters, 1990-07, Vol.11 (7), p.318-320

1990

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The effects of boron penetration on p+ polysilicon gated PMOS devices

IEEE transactions on electron devices, 1990-08, Vol.37 (8), p.1842-1851

1990

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A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

IEEE electron device letters, 1990-06, Vol.11 (6), p.253-255

1990

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Electrical properties of heavily doped polycrystalline silicon-germanium films

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

Anomalous co-diffusion effects of germanium on group III and V dopants in silicon

PMOS transistors in LPCVD polycrystalline silicon-germanium films

A self-aligned elevated source/drain MOSFET

Low-temperature annealing of arsenic/phosphorus junctions

An ultra-shallow buried-channel PMOST using boron penetration

LDD MOSFETs using disposable sidewall spacer technology

Gain-enhanced LDD NMOS device using cesium implantation

Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

The influence of tilted source-drain implants on high-field effects in submicrometer MOSFETs

A new technique for forming a shallow link base in a double polysilicon bipolar transistor

Improved CMOS field isolation using germanium/boron implantation

A novel CMOS VLSI isolation technology using selective chlorine implantation

Poly-gate sidewall oxidation induced submicrometer MOSFET degradation

A cobalt salicide CMOS process with TiN-strapped polysilicon gates

Improved MOSFET short-channel device using germanium implantation

Disposable polysilicon LDD spacer technology

An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

A novel PMOS SOI polysilicon transistor

Performance limits of CMOS ULSI

A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced 0.5- mu m CMOS disposable TiN LDD/salicide spacer process

The effects of boron penetration on p+ polysilicon gated PMOS devices

A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

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