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FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis

Journal of signal processing systems, 2023-10, Vol.95 (10), p.1245-1263

2023

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Editorial for the Special Issue on “Quantum-Dot Cellular Automata (QCA) and Low Power Application”

Journal of low power electronics and applications, 2018-12, Vol.8 (4), p.40

Perri, Stefania

2018

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Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation

IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.964-968

2019

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Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs

The Journal of supercomputing, 2024, Vol.80 (11), p.15894-15916

2024

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An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Sensors (Basel, Switzerland), 2019-07, Vol.19 (14), p.3055

2019

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Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes

Sensors (Basel, Switzerland), 2022-04, Vol.22 (8), p.2839

2022

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Design of Approximate Bilateral Filters for Image Denoising on FPGAs

IEEE access, 2023, Vol.11, p.1990-2000

2023

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Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors

Journal of low power electronics and applications, 2024-06, Vol.14 (2), p.24

2024

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Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems

IEEE access, 2022, Vol.10, p.7073-7081

2022

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Designing Energy-Efficient Approximate Multipliers

Journal of low power electronics and applications, 2022-12, Vol.12 (4), p.49

2022

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Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

Journal of low power electronics and applications, 2020-03, Vol.10 (1), p.1

2020

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Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

IEEE transactions on nanotechnology, 2014-03, Vol.13 (2), p.192-202

2014

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Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions

Journal of imaging, 2021-10, Vol.7 (10), p.210

2021

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Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

IEEE transactions on circuits and systems. I, Regular papers, 2014-05, Vol.61 (5), p.1456-1464

2014

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Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip

Journal of imaging, 2020-08, Vol.6 (9), p.85

2020

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An Efficient Connected Component Labeling Architecture for Embedded Systems

Journal of low power electronics and applications, 2018-03, Vol.8 (1), p.7

2018

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Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.1652-1656

2022

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Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

IEEE transactions on very large scale integration (VLSI) systems, 2015-02, Vol.23 (2), p.388-391

2015

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C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs

IEEE transactions on circuits and systems. I, Regular papers, 2024-08, p.1-12

2024

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A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.756-760

2023

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A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations

IEEE transactions on circuits and systems. II, Express briefs, 2024-06, p.1-1

2024

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Design of a Low-power Super-Resolution Architecture for Virtual Reality Wearable Devices

IEEE sensors journal, 2023-04, Vol.23 (8), p.1-1

2023

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Area-Delay Efficient Binary Adders in QCA

IEEE transactions on very large scale integration (VLSI) systems, 2014-05, Vol.22 (5), p.1174-1179

2014

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Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.3427-3431

2020

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Efficient implementation of signed multipliers on FPGAs

Computers & electrical engineering, 2024-05, Vol.116, p.109217, Article 109217

2024

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FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis

Editorial for the Special Issue on “Quantum-Dot Cellular Automata (QCA) and Low Power Application”

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation

Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes

Design of Approximate Bilateral Filters for Image Denoising on FPGAs

Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors

Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems

Designing Energy-Efficient Approximate Multipliers

Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip

An Efficient Connected Component Labeling Architecture for Embedded Systems

Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers

A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations

Design of a Low-power Super-Resolution Architecture for Virtual Reality Wearable Devices

Area-Delay Efficient Binary Adders in QCA

Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation

Efficient implementation of signed multipliers on FPGAs

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