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Detecting Affine Equivalence Of Boolean Functions And Circuit Transformation

Computer journal, 2023-09, Vol.66 (9), p.2220-2229

2023

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Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

IEEE transactions on nanotechnology, 2016-07, Vol.15 (4), p.675-686

2016

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Multi-input volistor logic XNOR gates

International journal of parallel, emergent and distributed systems, 2020-07, Vol.35 (4), p.423-432

2020

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A Group Algebraic Approach to NPN Classification of Boolean Functions

Theory of computing systems, 2019-08, Vol.63 (6), p.1278-1297

2019

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Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Journal of systems architecture, 2007-07, Vol.53 (7), p.453-464

2007

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Realization and synthesis of reversible functions

Theoretical computer science, 2011-04, Vol.412 (17), p.1606-1613

2011

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Fault Models for Quantum Mechanical Switching Networks

Journal of electronic testing, 2010-10, Vol.26 (5), p.499-511

2010

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Bi-Directional Synthesis of 4-Bit Reversible Circuits

Computer journal, 2008-03, Vol.51 (2), p.207-215

2008

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Exact synthesis of three-qubit quantum circuits from non-binary quantum gates

International journal of electronics, 2010-04, Vol.97 (4), p.475-489

2010

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Group Theory Based Synthesis of Binary Reversible Circuits

Lecture notes in computer science, 2006, p.365-374

2006

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Comparison of state assignment methods for "quantum circuit" model of permutative quantum state machines

IEEE Congress on Evolutionary Computation, 2010, p.1-8

2010

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A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures

IEEE transactions on very large scale integration (VLSI) systems, 2018-01, Vol.26 (1), p.23-36

2018

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On universality of general reversible multiple-valued logic gates

Proceedings. 34th International Symposium on Multiple-Valued Logic, 2004, p.68-73

2004

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Synthesis of reversible circuits with minimal costs

Calcolo, 2008-09, Vol.45 (3), p.193-206

2008

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Synthesizing hybrid quantum circuits without ancilla qudits

IEEE Congress on Evolutionary Computation, 2010, p.1-7

2010

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A minimal universal test set for self-test of EXOR-Sum-of-Products circuits

IEEE transactions on computers, 2000-03, Vol.49 (3), p.267-276

2000

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Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]

Proceedings. 34th International Symposium on Multiple-Valued Logic, 2004, p.58-67

2004

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Baldwinian learning utilizing genetic and heuristic algorithms for logic synthesis and minimization of incompletely specified data with Generalized Reed–Muller (AND–EXOR) forms

Journal of systems architecture, 2001-06, Vol.47 (6), p.477-489

2001

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Multi-valued functional decomposition as a machine learning method

Proceedings / International Symposium on Multiple-Valued Logic, 1998, p.173-178

1998

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Self-repairable GALs

Journal of systems architecture, 2001-02, Vol.47 (2), p.119-135

2001

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Bi-decompositions of multi-valued functions for circuit design and data mining applications

Proceedings / International Symposium on Multiple-Valued Logic, 1999, p.50-58

1999

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Fast synthesis of exact minimal reversible circuits using group theory

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, p.1002-1005

2005

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Functional decomposition of MVL functions using multi-valued decision diagrams

Proceedings / International Symposium on Multiple-Valued Logic, 1997, p.27-32

1997

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Minimal universal library for n × n reversible circuits

Computers & mathematics with applications (1987), 2008-07, Vol.56 (1), p.160-165

2008

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Highly testable Boolean ring logic circuits

Proceedings / International Symposium on Multiple-Valued Logic, 1999, p.268-274

1999

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Detecting Affine Equivalence Of Boolean Functions And Circuit Transformation

Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

Multi-input volistor logic XNOR gates

A Group Algebraic Approach to NPN Classification of Boolean Functions

Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Realization and synthesis of reversible functions

Fault Models for Quantum Mechanical Switching Networks

Bi-Directional Synthesis of 4-Bit Reversible Circuits

Exact synthesis of three-qubit quantum circuits from non-binary quantum gates

Group Theory Based Synthesis of Binary Reversible Circuits

Comparison of state assignment methods for "quantum circuit" model of permutative quantum state machines

A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures

On universality of general reversible multiple-valued logic gates

Synthesis of reversible circuits with minimal costs

Synthesizing hybrid quantum circuits without ancilla qudits

A minimal universal test set for self-test of EXOR-Sum-of-Products circuits

Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]

Baldwinian learning utilizing genetic and heuristic algorithms for logic synthesis and minimization of incompletely specified data with Generalized Reed–Muller (AND–EXOR) forms

Multi-valued functional decomposition as a machine learning method

Self-repairable GALs

Bi-decompositions of multi-valued functions for circuit design and data mining applications

Fast synthesis of exact minimal reversible circuits using group theory

Functional decomposition of MVL functions using multi-valued decision diagrams

Minimal universal library for n × n reversible circuits

Highly testable Boolean ring logic circuits

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