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Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-12, Vol.33 (12), p.1900-1913

2014

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Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1636-1648

2016

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Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning

IEEE transactions on very large scale integration (VLSI) systems, 2017-07, Vol.25 (7), p.2109-2117

2017

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Configurational Paths to Higher Efficiency in County Hospital: Evidence From Qualitative Comparative Analysis

Frontiers in public health, 2022-06, Vol.10, p.918571-918571

2022

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Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-12, Vol.34 (12), p.1964-1976

2015

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Impact of reimbursement rates on the length of stay in tertiary public hospitals: a retrospective cohort study in Shenzhen, China

BMJ open, 2020-11, Vol.10 (11), p.e040066-e040066

2020

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Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs

IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-06, Vol.7 (6), p.912-924

2017

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Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies

IEEE transactions on components, packaging, and manufacturing technology (2011), 2015-07, Vol.5 (7), p.980-990

2015

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Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Process

IEEE transactions on semiconductor manufacturing, 2017-05, Vol.30 (2), p.143-154

2017

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Fine-Grained 3-D IC Partitioning Study With a Multicore Processor

IEEE transactions on components, packaging, and manufacturing technology (2011), 2015-10, Vol.5 (10), p.1393-1401

2015

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Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-7

2013

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On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6

2014

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PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules

IEEE transactions on power electronics, 2021-08, Vol.36 (8), p.8919-8933

2021

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PowerSynth: A Power Module Layout Generation Tool

IEEE transactions on power electronics, 2019-06, Vol.34 (6), p.5063-5078

2019

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Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules

IEEE transactions on power electronics, 2023-04, Vol.38 (4), p.4698-4713

2023

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Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs

International Symposium on Low Power Electronics and Design (ISLPED), 2013, p.21-26

2013

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Holistic Chiplet-Package Co-Optimization for Agile Custom 2.5-D Design

IEEE transactions on components, packaging, and manufacturing technology (2011), 2021-05, Vol.11 (5), p.715-726

2021

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Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules

Journal of microelectronics and electronic packaging, 2023-10, Vol.20 (4)

2023

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Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8

2020

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Electronic Design Automation (EDA) Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules

2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020, p.5046-5052

2020

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PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization

2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), 2019, p.131-136

2019

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Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses

IEEE journal of emerging and selected topics in power electronics, 2023-12, Vol.11 (6), p.5613-5625

2023

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Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs

IEEE transactions on nanotechnology, 2018-07, Vol.17 (4), p.634-644

2018

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Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-8

2021

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Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs

Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning

Configurational Paths to Higher Efficiency in County Hospital: Evidence From Qualitative Comparative Analysis

Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling

Impact of reimbursement rates on the length of stay in tertiary public hospitals: a retrospective cohort study in Shenzhen, China

Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs

Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies

Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Process

Fine-Grained 3-D IC Partitioning Study With a Multicore Processor

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective

PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules

PowerSynth: A Power Module Layout Generation Tool

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules

Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs

Holistic Chiplet-Package Co-Optimization for Agile Custom 2.5-D Design

Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules

Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design

Electronic Design Automation (EDA) Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules

PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization

Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses

Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs

Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation

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