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A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

IEEE journal of solid-state circuits, 2017-11, Vol.52 (11), p.2843-2856

2017

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A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order ΣΔ Modulator

IEEE journal of solid-state circuits, 2012, Vol.47 (9), p.2107-2118

2012

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Active control of probability amplitudes in a mesoscale system via feedback-induced suppression of dissipation and noise

Journal of applied physics, 2016-12, Vol.120 (22)

2016

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Performance enhanced op-amp for 65nm CMOS technologies and below

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.201-204

2012

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A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order \Sigma \Delta Modulator

IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2107-2118

2012

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Use of time variant digital sigma-delta for fractional frequency synthesizers

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.169-172

2011

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A Simple Zero Average Switching Energy Differential SAR ADC

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-4

2024

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A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order [Formula Omitted] Modulator

IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2107

2012

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A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order capital sigma Delta Modulator

IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2107-2118

2012

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Reference Voltage Buffer for Hybrid RC-DAC SAR ADCs in 130 nm CMOS Process

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-4

2021

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Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator

IEEE transactions on circuits and systems. I, Regular papers, 2012-05, Vol.59 (5), p.969-978

2012

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Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Analog integrated circuits and signal processing, 2011-03, Vol.66 (3), p.381-388

2011

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Read-Out Architecture of CRYO System-on-Chip ASIC for Noble Liquid TPC Detectors

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.611-614

2020

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Analog sigma–delta modulation with Op-Amp gain compensation for nanometer technologies

Analog integrated circuits and signal processing, 2013-09, Vol.76 (3), p.297-305

2013

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Low-Noise Integrated Potentiostat for Affinity-Free Protein Detection With 12 nV/rt-Hz at 30 Hz and 1.8 pA rms Resolution

IEEE solid-state circuits letters, 2019-06, Vol.2 (6), p.41-44

2019

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Analog sigmaadelta modulation with Op-Amp gain compensation for nanometer technologies

Analog integrated circuits and signal processing, 2013-09, Vol.76 (3), p.297-305

2013

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Low-Noise Integrated Potentiostat for Affinity-Free Protein Detection With 12 nV/rt-Hz at 30 Hz and 1.8 pArms Resolution

IEEE solid-state circuits letters, 2019-06, Vol.2 (6), p.41-44

2019

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Slew-rate and gain enhancement in two stage operational amplifiers

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.2485-2488

2009

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Double-sampling analog-look-ahead second order ΣΔ modulator with reduced dynamics

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.2422-2425

2010

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27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.456-457

2017

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A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW

2011 IEEE International Solid-State Circuits Conference, 2011, p.478-480

2011

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Continuos Time ΣΔ modulator with efficient gain compensated integrators

Microelectronics, 2016-10, Vol.56, p.38-45

2016

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CRYO: a System-On-Chip ASIC for Noble Liquid TPC Experiments

2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2020, p.1-3

2020

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Design of a CMOS Compatible CFOA and its Application in Analog Filtering

Revista IEEE América Latina, 2007-05, Vol.5 (2), p.71-75

2007

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Digital Read-Out Modules of CRYO System-an-Chip ASIC for Cryogenic TPC Detectors

2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2020, p.1-2

2020

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A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order ΣΔ Modulator

Active control of probability amplitudes in a mesoscale system via feedback-induced suppression of dissipation and noise

Performance enhanced op-amp for 65nm CMOS technologies and below

A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order \Sigma \Delta Modulator

Use of time variant digital sigma-delta for fractional frequency synthesizers

A Simple Zero Average Switching Energy Differential SAR ADC

A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order [Formula Omitted] Modulator

A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order capital sigma Delta Modulator

Reference Voltage Buffer for Hybrid RC-DAC SAR ADCs in 130 nm CMOS Process

Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Read-Out Architecture of CRYO System-on-Chip ASIC for Noble Liquid TPC Detectors

Analog sigma–delta modulation with Op-Amp gain compensation for nanometer technologies

Low-Noise Integrated Potentiostat for Affinity-Free Protein Detection With 12 nV/rt-Hz at 30 Hz and 1.8 pA rms Resolution

Analog sigmaadelta modulation with Op-Amp gain compensation for nanometer technologies

Low-Noise Integrated Potentiostat for Affinity-Free Protein Detection With 12 nV/rt-Hz at 30 Hz and 1.8 pArms Resolution

Slew-rate and gain enhancement in two stage operational amplifiers

Double-sampling analog-look-ahead second order ΣΔ modulator with reduced dynamics

27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI

A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW

Continuos Time ΣΔ modulator with efficient gain compensated integrators

CRYO: a System-On-Chip ASIC for Noble Liquid TPC Experiments

Design of a CMOS Compatible CFOA and its Application in Analog Filtering

Digital Read-Out Modules of CRYO System-an-Chip ASIC for Cryogenic TPC Detectors

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