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Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

IEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.421-430

2018

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DIRT latch: A novel low cost double node upset tolerant latch

Microelectronics and reliability, 2017-01, Vol.68, p.57-68

2017

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A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Technologies (Basel), 2020-03, Vol.8 (1), p.6

2020

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Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

IEEE transactions on very large scale integration (VLSI) systems, 2016-10, Vol.24 (10), p.3105-3117

2016

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High Performance and Area Efficient Flexible DSP Datapath Synthesis

IEEE transactions on very large scale integration (VLSI) systems, 2011-03, Vol.19 (3), p.429-442

2011

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Walking through the Energy-Error Pareto Frontier of Approximate Multipliers

IEEE MICRO, 2018-07, Vol.38 (4), p.40-49

2018

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Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints

IEEE transactions on circuits and systems. II, Express briefs, 2019-04, Vol.66 (4), p.607-611

2019

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Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

ACM transactions on embedded computing systems, 2021-07, Vol.20 (5), p.1-21

2021

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Efficient design of magnitude and 2's complement comparators

Integration (Amsterdam), 2020-03, Vol.71, p.164-169

2020

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An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

IEEE transactions on circuits and systems. I, Regular papers, 2014-04, Vol.61 (4), p.1133-1143

2014

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VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2018-06, Vol.26 (6), p.1204-1208

2018

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Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers

2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, p.1-6

2019

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On the Diminished-1 Modulo 2n+1 Addition and Subtraction

Journal of circuits, systems, and computers, 2020-04, Vol.29 (5), p.2030005

2020

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Energy-efficient VLSI implementation of multipliers with double LSB operands

IET circuits, devices & systems, 2019-09, Vol.13 (6), p.816-821

2019

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Multiplexer-based array multipliers

IEEE transactions on computers, 1999-01, Vol.48 (1), p.15-23

Pekmestzi, K.Z.

1999

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Low latency radiation tolerant self-repair reconfigurable SRAM architecture

Microelectronics and reliability, 2016-01, Vol.56, p.202-211

2016

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A column parity based fault detection mechanism for FIFO buffers

Integration (Amsterdam), 2013-06, Vol.46 (3), p.265-279

2013

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Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.368-372

2016

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Cost Effective Protection Techniques for TCAM Memory Arrays

IEEE transactions on computers, 2012-12, Vol.61 (12), p.1778-1788

2012

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Delta DICE: A Double Node Upset resilient latch

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, p.1-4

2015

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Efficient Memory Repair Using Cache-Based Redundancy

IEEE transactions on very large scale integration (VLSI) systems, 2012-12, Vol.20 (12), p.2278-2288

2012

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Hybrid approximate multiplier architectures for improved power-accuracy trade-offs

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.79-84

2015

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Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

ACM transactions on design automation of electronic systems, 2013-01, Vol.18 (1), p.1-35

2013

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On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms

Information Security, 2001, Vol.2200, p.248-265

2001

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Efficient variability analysis of arithmetic units using linear regression techniques

Analog integrated circuits and signal processing, 2016-05, Vol.87 (2), p.249-261

2016

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Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

DIRT latch: A novel low cost double node upset tolerant latch

A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

High Performance and Area Efficient Flexible DSP Datapath Synthesis

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers

Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

Efficient design of magnitude and 2's complement comparators

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers

On the Diminished-1 Modulo 2n+1 Addition and Subtraction

Energy-efficient VLSI implementation of multipliers with double LSB operands

Multiplexer-based array multipliers

Low latency radiation tolerant self-repair reconfigurable SRAM architecture

A column parity based fault detection mechanism for FIFO buffers

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

Cost Effective Protection Techniques for TCAM Memory Arrays

Delta DICE: A Double Node Upset resilient latch

Efficient Memory Repair Using Cache-Based Redundancy

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms

Efficient variability analysis of arithmetic units using linear regression techniques

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