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Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4563-4567

2020

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Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures

IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2598-2604

2024

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K

Applied physics letters, 2020-06, Vol.116 (24)

2020

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Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Solid-state electronics, 2018-11, Vol.149, p.62-70

2018

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Probing Low-Frequency Charge Noise in Few-Electron CMOS Quantum Dots

Physical review applied, 2023-04, Vol.19 (4), Article 044010

2023

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Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

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Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation

Journal of Integrated Circuits and Systems, 2020-07, Vol.15 (2), p.1-5

2020

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Parity and Singlet-Triplet High-Fidelity Readout in a Silicon Double Quantum Dot at 0.5 K

PRX quantum, 2022-12, Vol.3 (4), p.040335, Article 040335

2022

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Electrical manipulation of a single electron spin in CMOS using a micromagnet and spin-valley coupling

npj quantum information, 2023-12, Vol.9 (1), p.107-7, Article 107

2023

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Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

IEEE journal of the Electron Devices Society, 2021, Vol.9, p.582-590

2021

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Analog performance of strained SOI nanowires down to 10K

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.222-225

2016

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(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI

ECS transactions, 2023-05, Vol.111 (1), p.149-160

2023

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Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

Solid-state electronics, 2021-12, Vol.186, p.108071, Article 108071

2021

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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

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Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Solid-state electronics, 2017-02, Vol.128, p.60-66

2017

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Spin-Valley Coupling Anisotropy and Noise in CMOS Quantum Dots

Physical review applied, 2022-03, Vol.17 (3), Article 034047

2022

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New method for individual electrical characterization of stacked SOI nanowire MOSFETs

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, p.1-3

2017

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Performance and transport analysis of vertically stacked p-FET SOI nanowires

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, p.79-82

2017

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Performance and Analysis of n-Type Vertically Stacked Nanowires Regarding Harmonic Distortion

Journal of Integrated Circuits and Systems, 2020-08, Vol.15 (2), p.1-5

2020

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Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, p.170-173

2016

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Electrical manipulation of a single electron spin in CMOS with micromagnet and spin-valley coupling

npj quantum information, 2023, Vol.9 (1)

2023

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Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

Microelectronics and reliability, 2013-06, Vol.53 (6), p.848-855

2013

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Non-linearity analysis of triple gate SOI nanowires MOSFETS

2016 31st Symposium on Microelectronics Technology and Devices (SBMicro), 2016, p.1-4

2016

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Improved continuous model for short channel double-gate junctionless transistors

2014 29th Symposium on Microelectronics Technology and Devices (SBMicro), 2014, p.1-4

2014

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Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures

Analog characteristics of n-type vertically stacked nanowires

Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Probing Low-Frequency Charge Noise in Few-Electron CMOS Quantum Dots

Electrical characterization of vertically stacked p-FET SOI nanowires

Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation

Parity and Singlet-Triplet High-Fidelity Readout in a Silicon Double Quantum Dot at 0.5 K

Electrical manipulation of a single electron spin in CMOS using a micromagnet and spin-valley coupling

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Analog performance of strained SOI nanowires down to 10K

(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI

Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Spin-Valley Coupling Anisotropy and Noise in CMOS Quantum Dots

New method for individual electrical characterization of stacked SOI nanowire MOSFETs

Performance and transport analysis of vertically stacked p-FET SOI nanowires

Performance and Analysis of n-Type Vertically Stacked Nanowires Regarding Harmonic Distortion

Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

Electrical manipulation of a single electron spin in CMOS with micromagnet and spin-valley coupling

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

Non-linearity analysis of triple gate SOI nanowires MOSFETS

Improved continuous model for short channel double-gate junctionless transistors

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