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Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

IEEE transactions on very large scale integration (VLSI) systems, 2006-07, Vol.14 (7), p.667-680

2006

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IEEE_Xplore

Force-directed scheduling for the behavioral synthesis of ASICs

IEEE transactions on computer-aided design of integrated circuits and systems, 1989-06, Vol.8 (6), p.661-679

1989

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IEEE_Xplore

System-on-chip beyond the nanometer wall

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003, p.419-424

2003

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IEEE_Xplore

StepNP: a system-level exploration platform for network processors

IEEE design & test of computers, 2002-11, Vol.19 (6), p.17-26

2002

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IEEE_Xplore

A Future of Customizable Processors: Are We There Yet?

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-2

2007

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IEEE_Xplore

DATE panel chips of the future: soft, crunchy or hard?

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.844-849 Vol.2

Paulin, P.G.

2004

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IEEE_Xplore

FlexWare: a retargetable, embedded-software development environment

IEEE design & test of computers, 2002-07, Vol.19 (4), p.59-69

2002

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IEEE_Xplore

Embedded software in real-time signal processing systems: design technologies

Proceedings of the IEEE, 1997-03, Vol.85 (3), p.436-454

1997

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IEEE_Xplore

Embedded software in real-time signal processing systems: application and architecture trends

Proceedings of the IEEE, 1997-03, Vol.85 (3), p.419-435

1997

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IEEE_Xplore

Towards application-specific architecture platforms: embedded systems design automation technologies

Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future, 2000, Vol.1, p.28-29

Paulin, P.G.

2000

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IEEE_Xplore

Distributed Object Models for Multi-Processor SoC's, with Application to Low-power Multimedia Wireless Systems

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-3

2006

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IEEE_Xplore

Application of a multi-processor SoC platform to high-speed packet forwarding

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.3, p.58-63 Vol.3

2004

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IEEE_Xplore

Network processors: a perspective on market requirements, processor architectures and embedded S/W tools

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.420-427

2001

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IEEE_Xplore

Algorithms for high-level synthesis

IEEE design & test of computers, 1989-12, Vol.6 (6), p.18-31

1989

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IEEE_Xplore

Network processing challenges and an experimental NPU platform [network processor unit]

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.64-69 suppl.

2003

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IEEE_Xplore

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

International Conference on Hardware Software Codesign: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis; 08-10 Sept. 2004, 2004, p.48-53

2004

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IEEE_Xplore

Designing high quality, scaleable SoC's with heterogeneous components

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720), 2004, p.325-325

Paulin, P.G.

2004

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Automatic mapping of parallel applications onto multi-processor platforms: a multimedia application

Euromicro Symposium on Digital System Design, 2004. DSD 2004, 2004, p.2-4

Paulin, P.G.

2004

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IEEE_Xplore

MPSoC memory optimization for digital camera applications

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007, p.424-427

2007

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IEEE_Xplore

HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis

23rd ACM/IEEE Design Automation Conference, 1986, p.263-270

1986

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IEEE_Xplore

Scheduling and binding algorithms for high-level synthesis

26th ACM/IEEE Design Automation Conference, 1989, p.1-6

1989

Link zum Volltext
IEEE_Xplore

Embedded systems technologies for application-specific architecture platforms

International Symposium on System Synthesis (IEEE Cat. No.01EX526), 2001, p.195-195

Paulin, Pierre G.

2001

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IEEE_Xplore

Horizontal partitioning of PLA-based finite state machines

26th ACM/IEEE Design Automation Conference, 1989, p.333-338

Paulin, P. G.

1989

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IEEE_Xplore

Logic decomposition algorithms for the timing optimization of multi-level logic

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989, p.329-333

1989

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IEEE_Xplore

Force-directed scheduling in automatic data path synthesis

24th ACM/IEEE Design Automation Conference, 1987, p.195-202

1987

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IEEE_Xplore

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Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

Force-directed scheduling for the behavioral synthesis of ASICs

System-on-chip beyond the nanometer wall

StepNP: a system-level exploration platform for network processors

A Future of Customizable Processors: Are We There Yet?

DATE panel chips of the future: soft, crunchy or hard?

FlexWare: a retargetable, embedded-software development environment

Embedded software in real-time signal processing systems: design technologies

Embedded software in real-time signal processing systems: application and architecture trends

Towards application-specific architecture platforms: embedded systems design automation technologies

Distributed Object Models for Multi-Processor SoC's, with Application to Low-power Multimedia Wireless Systems

Application of a multi-processor SoC platform to high-speed packet forwarding

Network processors: a perspective on market requirements, processor architectures and embedded S/W tools

Algorithms for high-level synthesis

Network processing challenges and an experimental NPU platform [network processor unit]

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

Designing high quality, scaleable SoC's with heterogeneous components

Automatic mapping of parallel applications onto multi-processor platforms: a multimedia application

MPSoC memory optimization for digital camera applications

HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis

Scheduling and binding algorithms for high-level synthesis

Embedded systems technologies for application-specific architecture platforms

Horizontal partitioning of PLA-based finite state machines

Logic decomposition algorithms for the timing optimization of multi-level logic

Force-directed scheduling in automatic data path synthesis

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