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Hybrid lithography process for nano-scale devices

Microelectronic engineering, 2006-04, Vol.83 (4), p.1761-1766

2006

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Sub- 30 ‐ nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2007-11, Vol.25 (6), p.2030-2033

2007

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Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2008-11, Vol.26 (6), p.2583-2586

2008

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Full three-dimensional characterization of 25 nm lines for chemically amplified resist simulation

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2005-11, Vol.23 (6), p.2733-2737

2005

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Improvement of high resolution lithography by using amorphous carbon hard mask

Microelectronic engineering, 2008-05, Vol.85 (5-6), p.800-804

2008

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High-Resolution Hybrid Lithography with Negative Tone Chemically Amplified Resists

Japanese Journal of Applied Physics, 2004-06, Vol.43 (6S), p.3974

2004

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Negative-tone chemically-amplified resist development for high resolution hybrid lithography

Microelectronic engineering, 2004-06, Vol.73, p.271-277

2004

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Negative-tone chemically-amplified resist development for high resolution hybrid lithography

Microelectronic engineering, 2004-06, Vol.73-74, p.271-277

2004

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(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

ECS transactions, 2016-05, Vol.72 (4), p.43-54

2016

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Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

2010 Symposium on VLSI Technology, 2010, p.193-194

2010

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Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2005-11, Vol.23 (6), p.3075-3079

2005

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Patterning Strategy for Monoelectronic Device Platform in a Complementary Metal Oxide Semiconductor Technology

Japanese Journal of Applied Physics, 2011-06, Vol.50 (6), p.06GF15-06GF15-5

2011

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Improvement of HfO2 based RRAM array performances by local Si implantation

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.14.6.1-14.6.4

2017

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15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

2008 IEEE International Electron Devices Meeting, 2008, p.1-4

2008

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Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, p.120-123

2017

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Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

ECS transactions, 2009, Vol.16 (10), p.923-934

2009

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Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

2011 International Electron Devices Meeting, 2011, p.9.5.1-9.5.4

2011

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A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

2009 IEEE International Electron Devices Meeting (IEDM), 2009, p.1-4

2009

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Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

2012 4th IEEE International Memory Workshop, 2012, p.1-4

2012

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Ultra high resolution hybrid lithography with negative tone chemically amplified resists

Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference, 2003, p.118-119

2003

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Full three-dimensional characterization of 25nm lines for chemically amplified resist simulation

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2005-11, Vol.23 (6), p.2733-2737

2005

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USIM in 5G Era

Journal of ICT Standardization, 2020-01, Vol.8 (1), p.29-40

Pauliac, Mireille

2020

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GaN wire-based Langmuir-Blodgett films for self-powered flexible strain sensors

Nanotechnology, 2014-09, Vol.25 (37), p.375502-8

2014

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Modeling metallic nanoparticle synthesis in a magnetron-based nanocluster source by gas condensation of a sputtered vapor

Journal of applied physics, 2010-03, Vol.107 (5), p.054309-054309-8

2010

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Flexible Capacitive Piezoelectric Sensor with Vertically Aligned Ultralong GaN Wires

ACS applied materials & interfaces, 2018-02, Vol.10 (5), p.4794-4800

2018

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Hybrid lithography process for nano-scale devices

Sub- 30 ‐ nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

Full three-dimensional characterization of 25 nm lines for chemically amplified resist simulation

Improvement of high resolution lithography by using amorphous carbon hard mask

High-Resolution Hybrid Lithography with Negative Tone Chemically Amplified Resists

Negative-tone chemically-amplified resist development for high resolution hybrid lithography

Negative-tone chemically-amplified resist development for high resolution hybrid lithography

(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

Patterning Strategy for Monoelectronic Device Platform in a Complementary Metal Oxide Semiconductor Technology

Improvement of HfO2 based RRAM array performances by local Si implantation

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes

Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

Ultra high resolution hybrid lithography with negative tone chemically amplified resists

Full three-dimensional characterization of 25nm lines for chemically amplified resist simulation

USIM in 5G Era

GaN wire-based Langmuir-Blodgett films for self-powered flexible strain sensors

Modeling metallic nanoparticle synthesis in a magnetron-based nanocluster source by gas condensation of a sputtered vapor

Flexible Capacitive Piezoelectric Sensor with Vertically Aligned Ultralong GaN Wires

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