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Runahead execution: an alternative to very large instruction windows for out-of-order processors

The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings, 2003, p.129-140

2003

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Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

IEEE MICRO, 2006-01, Vol.26 (1), p.10-20

2006

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Using system-level models to evaluate I/O subsystem designs

IEEE transactions on computers, 1998-06, Vol.47 (6), p.667-678

1998

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Runahead execution: An effective alternative to large instruction windows

IEEE MICRO, 2003-11, Vol.23 (6), p.20-25

2003

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An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors

IEEE transactions on computers, 2005-12, Vol.54 (12), p.1556-1571

2005

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Predicting Performance Impact of DVFS for Realistic Memory Systems

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.155-165

2012

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Prefetch-Aware Memory Controllers

IEEE transactions on computers, 2011-10, Vol.60 (10), p.1406-1430

2011

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MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.305-316

2012

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Wish Branches: Enabling Adaptive and Aggressive Predicated Execution

IEEE MICRO, 2006-01, Vol.26 (1), p.48-58

2006

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Disk arrays: high-performance, high-reliability storage subsystems

Computer (Long Beach, Calif.), 1994-03, Vol.27 (3), p.30-36

1994

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Evaluation of design options for the trace cache fetch mechanism

IEEE transactions on computers, 1999-02, Vol.48 (2), p.193-204

1999

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One billion transistors, one uniprocessor, one chip

Computer (Long Beach, Calif.), 1997-09, Vol.30 (9), p.51-57

1997

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Data Marshaling for Multicore Systems

IEEE MICRO, 2011-01, Vol.31 (1), p.56-64

2011

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Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware

IEEE transactions on computers, 2009-09, Vol.58 (9), p.1153-1170

2009

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Identifying Obstacles In The Path To More

Computer (Long Beach, Calif.), 1997-12, Vol.30 (12), p.32-32

Patt, Y.N.

1997

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Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching

IEEE MICRO, 2008-01, Vol.28 (1), p.91-98

2008

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An experimental single-chip data flow CPU

IEEE journal of solid-state circuits, 1992-01, Vol.27 (1), p.17-28

1992

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The V-Way Cache: Demand Based Associativity via Global Replacement

32nd International Symposium on Computer Architecture (ISCA'05), 2005, p.544-555

2005

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Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses

IEEE transactions on computers, 2006-12, Vol.55 (12), p.1491-1508

2006

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Using internal redundant representations and limited bypass to support pipelined adders and register files

Proceedings Eighth International Symposium on High Performance Computer Architecture, 2002, p.289-298

2002

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Energy Savings via Dead Sub-Block Prediction

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012, p.51-58

2012

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Single-Threaded vs. Multithreaded: Where Should We Focus?

IEEE MICRO, 2007-11, Vol.27 (6), p.14-24

2007

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Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication

IEEE MICRO, 2007-01, Vol.27 (1), p.94-104

2007

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Techniques for Efficient Processing in Runahead Execution Engines

32nd International Symposium on Computer Architecture (ISCA'05), 2005, p.370-381

2005

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Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution

International journal of parallel programming, 1997-10, Vol.25 (5), p.363-383

1997

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Runahead execution: an alternative to very large instruction windows for out-of-order processors

Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

Using system-level models to evaluate I/O subsystem designs

Runahead execution: An effective alternative to large instruction windows

An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors

Predicting Performance Impact of DVFS for Realistic Memory Systems

Prefetch-Aware Memory Controllers

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Wish Branches: Enabling Adaptive and Aggressive Predicated Execution

Disk arrays: high-performance, high-reliability storage subsystems

Evaluation of design options for the trace cache fetch mechanism

One billion transistors, one uniprocessor, one chip

Data Marshaling for Multicore Systems

Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware

Identifying Obstacles In The Path To More

Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching

An experimental single-chip data flow CPU

The V-Way Cache: Demand Based Associativity via Global Replacement

Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses

Using internal redundant representations and limited bypass to support pipelined adders and register files

Energy Savings via Dead Sub-Block Prediction

Single-Threaded vs. Multithreaded: Where Should We Focus?

Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication

Techniques for Efficient Processing in Runahead Execution Engines

Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution

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