UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Combined Static and Motion Features for Deep-Networks-Based Activity Recognition in Videos

IEEE transactions on circuits and systems for video technology, 2019-09, Vol.29 (9), p.2693-2707

2019

Volltextzugriff (PDF)

A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio

IEEE transactions on industrial electronics (1982), 2022-06, Vol.69 (6), p.5594-5603

2022

Volltextzugriff (PDF)

A Design Methodology to Synthesize First Degree Single-Path Hybrid DC-DC Converters

IEEE transactions on power electronics, 2022-10, Vol.37 (10), p.12336-12345

2022

Volltextzugriff (PDF)

4K Real-Time HEVC Decoder on an FPGA

IEEE transactions on circuits and systems for video technology, 2016-01, Vol.26 (1), p.236-249

2016

Volltextzugriff (PDF)

Nonisolated DC-DC Power Converter Synthesis Using Low-Entropy Equations

IEEE journal of emerging and selected topics in power electronics, 2022-12, Vol.10 (6), p.6457-6469

2022

Volltextzugriff (PDF)

HEVC inverse transform architecture utilizing coefficient sparsity

2015 IEEE International Conference on Image Processing (ICIP), 2015, p.4848-4852

2015

Volltextzugriff (PDF)

High performance parallel packet Classification architecture with Popular Rule Caching

2012 18th IEEE International Conference on Networks (ICON), 2012, p.52-57

2012

Volltextzugriff (PDF)

Towards Realtime Handheld MonoSLAM in Dynamic Environments

Advances in Visual Computing, 2011, p.313-324

2011

Volltextzugriff (PDF)

EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, p.81-84

2018

Volltextzugriff (PDF)

A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform

2018 21st Euromicro Conference on Digital System Design (DSD), 2018, p.472-478

2018

Volltextzugriff (PDF)

Real time all intra HEVC HD encoder on FPGA

2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016, p.191-195

2016

Volltextzugriff (PDF)

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019, p.117-117

2019

Volltextzugriff (PDF)

Line rate parallel packet classification module for NetFPGA platform

2013 IEEE 8th International Conference on Industrial and Information Systems, 2013, p.277-282

2013

Volltextzugriff (PDF)

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks

2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, p.1-7

2018

Volltextzugriff (PDF)

FPAA and FPGA based universal sensor node design

2017 Eleventh International Conference on Sensing Technology (ICST), 2017, p.1-6

2017

Volltextzugriff (PDF)

FPGA IP for Real-time 4K HDR Image Decoding in VR Devices

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 2019, p.101-104

2019

Volltextzugriff (PDF)

VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing

2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, Vol.2160-052X, p.103-106

2019

Volltextzugriff (PDF)

A generalized preprocessing and feature extraction platform for scalp EEG signals on FPGA

2014 IEEE Conference on Biomedical Engineering and Sciences (IECBES), 2014, p.137-142

2014

Volltextzugriff (PDF)

SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks

2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, Vol.2160-052X, p.235-238

2019

Volltextzugriff (PDF)

FPGA based custom accelerator architecture framework for complex event processing

TENCON 2014 - 2014 IEEE Region 10 Conference, 2014, p.1-6

2014

Volltextzugriff (PDF)

High performance flow matching architecture for OpenFlow data plane

2016 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2016, p.186-191

2016

Volltextzugriff (PDF)

Runtime rule-reconfigurable high throughput NIPS on FPGA

2017 International Conference on Field Programmable Technology (ICFPT), 2017, p.251-254

2017

Volltextzugriff (PDF)

Micro Actions and Deep Static Features for Activity Recognition

2017 International Conference on Digital Image Computing: Techniques and Applications (DICTA), 2017, p.1-8

2017

Volltextzugriff (PDF)

An Analytical Method to Derive a DC-DC Converter for an Arbitrary Voltage Conversion Ratio

2018 8th International Conference on Power and Energy Systems (ICPES), 2018, p.11-16

2018

Volltextzugriff (PDF)

Online classification of imagined hand movement using a consumer grade EEG device

2013 IEEE 8th International Conference on Industrial and Information Systems, 2013, p.537-541

2013

Volltextzugriff (PDF)

1 – 25 von 33

Menü

Weitere Dienste

Einstellungen

Combined Static and Motion Features for Deep-Networks-Based Activity Recognition in Videos

A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio

A Design Methodology to Synthesize First Degree Single-Path Hybrid DC-DC Converters

4K Real-Time HEVC Decoder on an FPGA

Nonisolated DC-DC Power Converter Synthesis Using Low-Entropy Equations

HEVC inverse transform architecture utilizing coefficient sparsity

High performance parallel packet Classification architecture with Popular Rule Caching

Towards Realtime Handheld MonoSLAM in Dynamic Environments

EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA

A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform

Real time all intra HEVC HD encoder on FPGA

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks

Line rate parallel packet classification module for NetFPGA platform

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks

FPAA and FPGA based universal sensor node design

FPGA IP for Real-time 4K HDR Image Decoding in VR Devices

VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing

A generalized preprocessing and feature extraction platform for scalp EEG signals on FPGA

SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks

FPGA based custom accelerator architecture framework for complex event processing

High performance flow matching architecture for OpenFlow data plane

Runtime rule-reconfigurable high throughput NIPS on FPGA

Micro Actions and Deep Static Features for Activity Recognition

An Analytical Method to Derive a DC-DC Converter for an Arbitrary Voltage Conversion Ratio

Online classification of imagined hand movement using a consumer grade EEG device

Suchergebnisse filtern