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The associations of fibroblast growth factor 23 and uncarboxylated matrix Gla protein with mortality in coronary artery disease: the Heart and Soul Study

Annals of internal medicine, 2010-05, Vol.152 (10), p.640

2010

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Integrated Self-Healing for mm-Wave Power Amplifiers

IEEE transactions on microwave theory and techniques, 2013-03, Vol.61 (3), p.1301-1315

2013

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IEEE_Xplore

Black School Closings Aren’t New: Historically Contextualizing Contemporary School Closings and Black Community Resistance

Educational Researcher, 2022-12, Vol.51 (9), p.575-583

2022

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Association of Osteocalcin and Abdominal Aortic Calcification in Older Women: The Study of Osteoporotic Fractures

Calcified tissue international, 2010-03, Vol.86 (3), p.185-191

2010

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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

IEEE journal of solid-state circuits, 2013-05, Vol.48 (5), p.1138-1150

2013

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IEEE_Xplore

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

IEEE journal of solid-state circuits, 2006-12, Vol.41 (12), p.2885-2900

2006

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IEEE_Xplore

A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1744-1755

2016

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IEEE_Xplore

Association of kidney function and uncarboxylated matrix Gla protein: Data from the Heart and Soul Study

Nephrology, dialysis, transplantation, 2009-07, Vol.24 (7), p.2095-2101

2009

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The association of uncarboxylated matrix Gla protein with mitral annular calcification differs by diabetes status: The Heart and Soul study

Atherosclerosis, 2010-05, Vol.210 (1), p.320-325

2010

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Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"

IEEE journal of solid-state circuits, 2013-06, Vol.48 (6), p.1539-1539

2013

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IEEE_Xplore

W-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS

IEEE transactions on microwave theory and techniques, 2015-06, Vol.63 (6), p.1989-2002

2015

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IEEE_Xplore

Schools as Discriminatory Artifacts

Perspectives on urban education, 2016, Vol.13 (1), p.76

Parker, Benjamin D

2016

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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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IEEE_Xplore

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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IEEE_Xplore

A 1.8 pJ/bit [Formula Omitted] Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1744

2016

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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2013-08, Vol.60 (8), p.2009-2017

2013

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IEEE_Xplore

A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.368-369,369a

2009

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IEEE_Xplore

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, p.1-4

2014

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IEEE_Xplore

Race, Community, and Urban Schools: Partnering with African American Families

Journal of Language and Literacy Education, 2015, Vol.11 (2), p.206

Parker, Benjamin D

2015

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CRT In Education: Historical/Archival Analyses

Understanding Critical Race Research Methods and Methodologies, 2019, p.24-33

1, 2019

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A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-4

2015

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IEEE_Xplore

Environmental performance of blue foods

Nature (London), 2021-09, Vol.597 (7876), p.360-365

2021

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Single-Neuron Sequencing Analysis of L1 Retrotransposition and Somatic Mutation in the Human Brain

Cell, 2012-10, Vol.151 (3), p.483-496

2012

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Cell profiling of mouse acute kidney injury reveals conserved cellular responses to injury

Proceedings of the National Academy of Sciences - PNAS, 2020-07, Vol.117 (27), p.15874-15883

2020

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The associations of fibroblast growth factor 23 and uncarboxylated matrix Gla protein with mortality in coronary artery disease: the Heart and Soul Study

Integrated Self-Healing for mm-Wave Power Amplifiers

Black School Closings Aren’t New: Historically Contextualizing Contemporary School Closings and Black Community Resistance

Association of Osteocalcin and Abdominal Aortic Calcification in Older Women: The Study of Osteoporotic Fractures

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

Association of kidney function and uncarboxylated matrix Gla protein: Data from the Heart and Soul Study

The association of uncarboxylated matrix Gla protein with mitral annular calcification differs by diabetes status: The Heart and Soul study

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"

W-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS

Schools as Discriminatory Artifacts

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

A 1.8 pJ/bit [Formula Omitted] Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Race, Community, and Urban Schools: Partnering with African American Families

CRT In Education: Historical/Archival Analyses

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Environmental performance of blue foods

Single-Neuron Sequencing Analysis of L1 Retrotransposition and Somatic Mutation in the Human Brain

Cell profiling of mouse acute kidney injury reveals conserved cellular responses to injury

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