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An efficient test data reduction technique through dynamic pattern mixing across multiple fault models

29th VLSI Test Symposium, 2011, p.285-290

2011

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Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-11, Vol.31 (11), p.1754-1766

2012

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Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

2011 Asian Test Symposium, 2011, p.33-39

2011

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Derating based hardware optimizations in soft error tolerant designs

2012 IEEE 30th VLSI Test Symposium (VTS), 2012, p.282-287

2012

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Multi-CoDec Configurations for Low Power and High Quality Scan Test

2011 24th Internatioal Conference on VLSI Design, 2011, p.370-375

2011

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DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management

2011 IEEE International Test Conference, 2011, p.1-10

2011

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Power Analysis and Reduction Techniques for Transition Fault Testing

2008 17th Asian Test Symposium, 2008, p.403-408

2008

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Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage

2009 Asian Test Symposium, 2009, p.331-336

2009

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A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips

26th IEEE VLSI Test Symposium (vts 2008), 2008, p.53-58

2008

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Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.339-344

2007

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Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency

14th Asian Test Symposium (ATS'05), 2005, p.330-336

2005

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Monitoring machine based synthesis technique for concurrent error detection in finite state machines

Journal of electronic testing, 1996-04, Vol.8 (2), p.179-201

1996

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DFT for test optimisations in a complex mixed-signal SOC - case study on TI's TNETD7300 ADSL modem device

2004 International Conferce on Test, 2004, p.773-782

2004

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Concurrent error detection using monitoring machines

IEEE design & test of computers, 1995, Vol.12 (3), p.24

1995

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Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

2012 17th IEEE European Test Symposium (ETS), 2012, p.1-6

2012

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Design methodology and microdiagnostics development for a self-checking microprocessor

International Symposium on Microarchitecture: Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture; 14-16 Aug. 1989, 1989, p.70-82

1989

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DFT for Low Cost SOC Test

14th Asian Test Symposium (ATS'05), 2005, p.451-451

Parekhji, R.A.

2005

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Reduced overhead soft error mitigation using error control coding techniques

2011 IEEE 17th International On-Line Testing Symposium, 2011, p.163-168

2011

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Panel synopsis - how (In)adequate is one time testing?

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.1279-1279

Parekhji, R.A.

2003

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Testing embedded cores and SOCs-DFT, ATPG and BIST solutions

16th International Conference on VLSI Design, 2003. Proceedings, 2003, p.17

Parekhji, R.A.

2003

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Methodology for low power test pattern generation using activity threshold control logic

2007 IEEE/ACM International Conference on Computer-Aided Design, 2007, p.526-529

2007

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A systematic approach to synthesis of verification test-suites for modular SoC designs

2008 IEEE International SOC Conference, 2008, p.91-96

2008

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Design methodology and microdiagnostics development for a self-checking microprocessor

MICRO-22: Microprogramming and Microarchitecture Workshop, 1989-09, Vol.20 (3), p.70-82

1989

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E-groups: a new technique for fast backward propagation in system-level test generation

Proceedings of the Fifth Asian Test Symposium (ATS'96), 1996, p.34-41

1996

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Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems

Proceedings - Asian Test Symposium, 2000, p.260-266

2000

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An efficient test data reduction technique through dynamic pattern mixing across multiple fault models

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

Derating based hardware optimizations in soft error tolerant designs

Multi-CoDec Configurations for Low Power and High Quality Scan Test

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management

Power Analysis and Reduction Techniques for Transition Fault Testing

Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips

Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

DFT for test optimisations in a complex mixed-signal SOC - case study on TI's TNETD7300 ADSL modem device

Concurrent error detection using monitoring machines

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

Design methodology and microdiagnostics development for a self-checking microprocessor

DFT for Low Cost SOC Test

Reduced overhead soft error mitigation using error control coding techniques

Panel synopsis - how (In)adequate is one time testing?

Testing embedded cores and SOCs-DFT, ATPG and BIST solutions

Methodology for low power test pattern generation using activity threshold control logic

A systematic approach to synthesis of verification test-suites for modular SoC designs

Design methodology and microdiagnostics development for a self-checking microprocessor

E-groups: a new technique for fast backward propagation in system-level test generation

Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems

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