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A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed

IEEE transactions on industrial electronics (1982), 2017-02, Vol.64 (2), p.1233-1240

2017

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A portable digitally controlled oscillator using novel varactors

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2005-05, Vol.52 (5), p.233-237

2005

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A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

IEEE journal of solid-state circuits, 2006-06, Vol.41 (6), p.1275-1285

2006

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An Interpolated Flying-Adder-Based Frequency Synthesizer

Journal of Electrical and Computer Engineering, 2011-01, Vol.2011, p.1-11

2011

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Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop

2008 IEEE International Symposium on Circuits and Systems, 2008, p.2554-2557

Chen, Pao-Lung

2008

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A low-cost carry look-ahead adder for flying-adder frequency synthesizer

2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2016, p.1-2

Pao-Lung Chen

2016

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An open-loop fractional divider based on direct phase synthesis

2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2016, p.1-2

Pao-Lung Chen

2016

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An Inductorless Chua's Circuit with Memristor

2015 2nd International Conference on Information Science and Control Engineering, 2015, p.616-619

Pao-Lung Chen

2015

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Carry randomization with fractional control of a De Bruijn sequence

2015 IEEE International Conference on Consumer Electronics - Taiwan, 2015, p.448-449

Pao-Lung Chen

2015

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A Fully Synthesizable Ultra- Audio Frequency Multiplier for HDMI Applications

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.2134-2138

Chen, Pao-Lung

2020

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An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering

2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019, p.1-2

Chen, Pao-Lung

2019

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Digitally controlled oscillator with storage based randomization for spurs reduction

2015 IEEE International Conference on Consumer Electronics - Taiwan, 2015, p.450-451

2015

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Simulation-Based Analysis and Experimental Verification of Chaotic Circuits

Next Wave in Robotics, p.155-161

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A fractional pseudo random binary sequence for spur reduction in flying-adder frequency synthesizer

2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014, Vol.1, p.241-244

2014

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A multiphase delay-locked loop with interleaving calibration

2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014, Vol.1, p.237-240

2014

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A low power multiphase all-digital phase locked loop with reusing SAR

The 2010 International Conference on Green Circuits and Systems, 2010, p.695-698

Pao-Lung Chen

2010

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An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.4875-4878 Vol. 5

2005

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A multiphase all-digital delay-locked loop with reuse SAR

2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010, p.943-946

2010

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An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications

2006 International Symposium on VLSI Design, Automation and Test, 2006, p.1-4

2006

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A jumping algorithm for calibration in multiphase delay locked loop

2013 10th IEEE International Conference on Control and Automation (ICCA), 2013, p.1065-1069

Chen, Pao-Lung

2013

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A Cost-Effective TAF-DPS Syntonization Scheme of Improving Clock Frequency Accuracy and Long-Term Frequency Stability for Universal Applications

Low-Power Circuits for Emerging Applications in Communications, Computing, and Sensing, 2019, p.97-120

1, 2019

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Genetic profiles of 103,106 individuals in the Taiwan Biobank provide insights into the health and history of Han Chinese

Npj genomic medicine, 2021-02, Vol.6 (1), p.10-10, Article 10

2021

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A compact software-controlled clock multiplier for SoC application

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, 2002, Vol.1, p.I-499

2002

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Marginalization or risk aversion? Using big data to examine why women are found to be less corrupt in court judgments

Governance (Oxford), 2024-01, Vol.37 (1), p.79-98

2024

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Neutralization of CX3CL1 Attenuates TGF-β-Induced Fibroblast Differentiation Through NF-κB Activation and Mitochondrial Dysfunction in Airway Fibrosis

Lung, 2024-06, Vol.202 (3), p.343-356

2024

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A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed

A portable digitally controlled oscillator using novel varactors

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

An Interpolated Flying-Adder-Based Frequency Synthesizer

Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop

A low-cost carry look-ahead adder for flying-adder frequency synthesizer

An open-loop fractional divider based on direct phase synthesis

An Inductorless Chua's Circuit with Memristor

Carry randomization with fractional control of a De Bruijn sequence

A Fully Synthesizable Ultra- Audio Frequency Multiplier for HDMI Applications

An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering

Digitally controlled oscillator with storage based randomization for spurs reduction

Simulation-Based Analysis and Experimental Verification of Chaotic Circuits

A fractional pseudo random binary sequence for spur reduction in flying-adder frequency synthesizer

A multiphase delay-locked loop with interleaving calibration

A low power multiphase all-digital phase locked loop with reusing SAR

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications

A multiphase all-digital delay-locked loop with reuse SAR

An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications

A jumping algorithm for calibration in multiphase delay locked loop

A Cost-Effective TAF-DPS Syntonization Scheme of Improving Clock Frequency Accuracy and Long-Term Frequency Stability for Universal Applications

Genetic profiles of 103,106 individuals in the Taiwan Biobank provide insights into the health and history of Han Chinese

A compact software-controlled clock multiplier for SoC application

Marginalization or risk aversion? Using big data to examine why women are found to be less corrupt in court judgments

Neutralization of CX3CL1 Attenuates TGF-β-Induced Fibroblast Differentiation Through NF-κB Activation and Mitochondrial Dysfunction in Airway Fibrosis

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