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Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters

IEEE transactions on very large scale integration (VLSI) systems, 2017-08, Vol.25 (8), p.2234-2247

2017

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High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1757-1762

2017

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A Statistical Model for Simulating the Effect of LTPS TFT Device Variation for SOP Applications

Journal of display technology, 2007-12, Vol.3 (4), p.426-433

2007

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An integrated placement and routing for ratioed capacitor array based on ILP formulation

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2016, p.1-4

2016

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Statistical study on the states in the low-temperature poly-silicon films with thin film transistors

Thin solid films, 2006-11, Vol.515 (3), p.1210-1213

2006

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Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011, p.512-516

2011

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A corner stitching compliant B∗-tree representation and its applications to analog placement

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011, p.507-511

2011

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Heterogeneous B-trees for analog placement with symmetry and regularity considerations

Proceedings of the International Conference on Computer-Aided Design, 2011, p.512-516

2011

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A corner stitching compliant B-tree representation and its applications to analog placement

Proceedings of the International Conference on Computer-Aided Design, 2011, p.507-511

2011

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Subtlety and Sophistication

Major Lyricists of the Northern Sung: 960-1126 A.D, 2015, p.161

Chou Pang-yen

2015

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Hepatic and Systemic Inflammation for Left Ventricular Mass in Physically Fit Adults: CHIEF Heart Study

Endocrine, metabolic & immune disorders drug targets, 2023-01, Vol.23 (7), p.977-983

2023

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Neutrophil-Lymphocyte Ratio as a Predictor of Cerebral Small Vessel Disease in a Geriatric Community: The I-Lan Longitudinal Aging Study

Brain sciences, 2023-07, Vol.13 (7), p.1087

2023

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2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Circuits, systems, and signal processing, 2021-06, Vol.40 (6), p.2824-2840

2021

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NT-proBNP point-of-care testing for predicting mortality in end-stage renal disease: A survival analysis

Heliyon, 2024-05, Vol.10 (9), p.e30581-e30581, Article e30581

2024

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Stratifying the Optimal Thresholds of Point-Of-Care Testing NT-proBNP as Acute Heart Failure Marker in Elder Patients with Impaired Kidney Function

International Journal of Gerontology, 2023-01, Vol.17 (1)

2023

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2$$\times $$VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Circuits, systems, and signal processing, 2021-06, Vol.40 (6), p.2824-2840

2021

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Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.16-17

2005

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Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters

High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC

A Statistical Model for Simulating the Effect of LTPS TFT Device Variation for SOP Applications

An integrated placement and routing for ratioed capacitor array based on ILP formulation

Statistical study on the states in the low-temperature poly-silicon films with thin film transistors

Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations

A corner stitching compliant B∗-tree representation and its applications to analog placement

Heterogeneous B-trees for analog placement with symmetry and regularity considerations

A corner stitching compliant B-tree representation and its applications to analog placement

Subtlety and Sophistication

Hepatic and Systemic Inflammation for Left Ventricular Mass in Physically Fit Adults: CHIEF Heart Study

Neutrophil-Lymphocyte Ratio as a Predictor of Cerebral Small Vessel Disease in a Geriatric Community: The I-Lan Longitudinal Aging Study

2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

NT-proBNP point-of-care testing for predicting mortality in end-stage renal disease: A survival analysis

Stratifying the Optimal Thresholds of Point-Of-Care Testing NT-proBNP as Acute Heart Failure Marker in Elder Patients with Impaired Kidney Function

2$$\times $$VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

2024 Guidelines of the Taiwan Society of Cardiology on the Primary Prevention of Atherosclerotic Cardiovascular Disease --- Part I

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

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