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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

IEEE transactions on very large scale integration (VLSI) systems, 2018-04, Vol.26 (4), p.639-652

2018

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VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, p.26-38

2015

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Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality

Proceedings of the IEEE, 2018-11, Vol.106 (11), p.2020-2039

2018

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A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures

ACM transactions on architecture and code optimization, 2020-11, Vol.17 (4), p.1-30

2020

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FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit

Microprocessors and microsystems, 2023-03, Vol.97, p.104762, Article 104762

2023

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Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

ACM transactions on architecture and code optimization, 2023-03, Vol.20 (2), p.1-25, Article 28

2023

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EVX: Vector execution on low power EDGE cores

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, p.1-4

2014

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Architectural support for efficient message passing on shared memory multi-cores

Journal of parallel and distributed computing, 2016-09, Vol.95, p.92-106

2016

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Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory

Computing in science & engineering, 2016-01, Vol.18 (1), p.80-87

2016

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Memory Controller for Vector Processor

Journal of signal processing systems, 2018-11, Vol.90 (11), p.1533-1549

2018

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Reusing cached schedules in an out-of-order processor with in-order issue logic

2009 IEEE International Conference on Computer Design, 2009, p.246-253

2009

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DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores

2015 44th International Conference on Parallel Processing, 2015, p.130-139

2015

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Future Vector Microprocessor Extensions for Data Aggregations

2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016, p.418-430

2016

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ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Microprocessors and microsystems, 2015-11, Vol.39 (8), p.1174-1189

2015

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Vector Extensions for Decision Support DBMS Acceleration

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.166-176

2012

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Advanced Pattern based Memory Controller for FPGA based HPC applications

2014 International Conference on High Performance Computing & Simulation (HPCS), 2014, p.287-294

2014

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POSTER: An integrated vector-scalar design on an in-order ARM core

2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), 2016, p.447-448

2016

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EVX: vector execution on low power EDGE cores

Proceedings of the conference on Design, Automation & Test in Europe, 2014, p.1-4

2014

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VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014, p.1-8

2014

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Energy minimization at all layers of the data center: The ParaDIME project

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.684-689

2016

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Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi

2014 International Conference on High Performance Computing & Simulation (HPCS), 2014, p.47-54

2014

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MAPC: Memory access pattern based controller

2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, p.1-4

2014

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Runtime-Aware Architectures

Euro-Par 2015: Parallel Processing, 2015, p.16-27

2015

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VALib and SimpleVector: tools for rapid initial research on vector architectures

Proceedings of the 11th ACM Conference on Computing Frontiers, 2014, p.1-10

2014

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Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders

2014 IEEE Computer Society Annual Symposium on VLSI, 2014, p.118-123

2014

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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

EVX: Vector execution on low power EDGE cores

Architectural support for efficient message passing on shared memory multi-cores

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory

Memory Controller for Vector Processor

Reusing cached schedules in an out-of-order processor with in-order issue logic

DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores

Future Vector Microprocessor Extensions for Data Aggregations

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Vector Extensions for Decision Support DBMS Acceleration

Advanced Pattern based Memory Controller for FPGA based HPC applications

POSTER: An integrated vector-scalar design on an in-order ARM core

EVX: vector execution on low power EDGE cores

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Energy minimization at all layers of the data center: The ParaDIME project

Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi

MAPC: Memory access pattern based controller

Runtime-Aware Architectures

VALib and SimpleVector: tools for rapid initial research on vector architectures

Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders

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