UB Paderborn / Katalog / Suche / in CDI

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.498-503

Perrott, Michael H.

2002

Link zum Volltext

Verfügbarkeit prüfen

A 12-Bit, 10-MHz Bandwidth, Continuous-Time \Sigma\Delta ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.805-814

2008

Link zum Volltext
IEEE_Xplore

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

IEEE journal of solid-state circuits, 1997-12, Vol.32 (12), p.2048-2060

1997

Link zum Volltext
IEEE_Xplore

A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation

IEEE journal of solid-state circuits, 2006-02, Vol.41 (2), p.443-451

2006

Link zum Volltext

Verfügbarkeit prüfen

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator

IEEE journal of solid-state circuits, 2010-12, Vol.45 (12), p.2566-2581

2010

Link zum Volltext
IEEE_Xplore

A Time-Domain Resolution Improvement of an RF-DAC

IEEE transactions on circuits and systems. II, Express briefs, 2010-07, Vol.57 (7), p.517-521

2010

Link zum Volltext
IEEE_Xplore

A Low-Noise Wide-BW 3.6-GHz Digital \Delta\Sigma Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

IEEE journal of solid-state circuits, 2008-12, Vol.43 (12), p.2776-2786

2008

Link zum Volltext
IEEE_Xplore

A 2.5-Gb/s multi-rate-0.25-μm CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition

IEEE journal of solid-state circuits, 2006-12, Vol.41 (12), p.2930-2944

2006

Link zum Volltext

Verfügbarkeit prüfen

A multiphase PWM RF modulator using a VCO-based opamp in 45nm CMOS

2010 IEEE Radio Frequency Integrated Circuits Symposium, 2010, p.39-42

2010

Link zum Volltext
IEEE_Xplore

A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis

IEEE journal of solid-state circuits, 2002-08, Vol.37 (8), p.1028-1038

2002

Link zum Volltext

Verfügbarkeit prüfen

An efficient approach to ARMA modeling of biological systems with multiple inputs and delays

IEEE transactions on biomedical engineering, 1996-01, Vol.43 (1), p.1-14

1996

Link zum Volltext
IEEE_Xplore

A 0.5 V $< \hbox{4}\ \mu$ W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor

IEEE journal of solid-state circuits, 2014-01, Vol.49 (1), p.271-288

2014

Link zum Volltext

Verfügbarkeit prüfen

A 0.5 V $W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor

IEEE journal of solid-state circuits, 2014-01, Vol.49 (1), p.271-288

2014

Link zum Volltext
IEEE_Xplore

A clockless, multi-stable, CMOS analog circuit

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1764-1767

2014

Link zum Volltext
IEEE_Xplore

DL Michael H. Perrott Speaks on System-Level Simulation of Time-Based Circuits and Digital PLLs at SSCS Lehigh Valley [Chapters]

IEEE solid state circuits magazine, 2014-03, Vol.6 (1), p.63-66

2014

Link zum Volltext
IEEE_Xplore

1 – 25 von 63

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(39)
Mit Volltextzugriff
(60)

Publikationsform

Sprache

Englisch
(63)
Japanisch
(4)

Erscheinungsjahr

n.n

Thema

Science & Technology
(40)
Technology
(33)
Engineering
(32)
Engineering, Electrical & Electronic
(30)
Quantization
(16)
Phase Locked Loops
(13)
Circuits
(12)
Noise Shaping
(12)
Applied Sciences
(11)
Electronics
(11)
Exact Sciences And Technology
(11)
Frequency Synthesizers
(11)
Noise
(11)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(11)
Circuit Properties
(10)
Electric, Optical And Optoelectronic Circuits
(10)
Electronic Circuits
(10)
Prototypes
(10)
Integrated Circuits
(9)
Oscillators, Resonators, Synthetizers
(9)

15 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping

A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter

Photonic subsampling analog-to-digital conversion of microwave signals at 40-GHz with higher than 7-ENOB resolution

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

A 12-Bit, 10-MHz Bandwidth, Continuous-Time \Sigma\Delta ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator

A Time-Domain Resolution Improvement of an RF-DAC

A Low-Noise Wide-BW 3.6-GHz Digital \Delta\Sigma Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

A 2.5-Gb/s multi-rate-0.25-μm CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition

A multiphase PWM RF modulator using a VCO-based opamp in 45nm CMOS

A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis

An efficient approach to ARMA modeling of biological systems with multiple inputs and delays

A 0.5 V $< \hbox{4}\ \mu$ W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor

A 0.5 V $W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor

A clockless, multi-stable, CMOS analog circuit

DL Michael H. Perrott Speaks on System-Level Simulation of Time-Based Circuits and Digital PLLs at SSCS Lehigh Valley [Chapters]

Suchergebnisse filtern