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Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums

Journal of electronic testing, 2020-12, Vol.36 (6), p.703-718

2020

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Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.3250-3262

2020

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Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1

2022

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Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1147-1160

2023

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SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks

ACM transactions on embedded computing systems, 2021-10, Vol.20 (5s), p.1-25, Article 76

2021

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Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

2019 IEEE 28th Asian Test Symposium (ATS), 2019, p.7-75

2019

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The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures

Architecture of Computing Systems – ARCS 2019, p.253-266

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Just say zero: containing critical bit-error propagation in deep neural networks with anomalous feature suppression

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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SNR: S queezing N umerical R ange Defuses Bit Error Vulnerability Surface in Deep Neural Networks

ACM transactions on embedded computing systems, 2021-10, Vol.20 (5s), p.1-25

2021

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Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-8

2021

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Squeezing Correlated Neurons for Resource-Efficient Deep Neural Networks

Machine Learning and Knowledge Discovery in Databases, p.52-68

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Algorithm-Centric Design of Reliable and Efficient Deep Learning Processing Systems

Ozen, Elbruz

2023

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Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, p.169-174

2020

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Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation

IEEE design and test, 2023-04, Vol.40 (2), p.59-66

2023

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Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums

Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection

Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation

Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks

Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures

Just say zero: containing critical bit-error propagation in deep neural networks with anomalous feature suppression

SNR: S queezing N umerical R ange Defuses Bit Error Vulnerability Surface in Deep Neural Networks

Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs

Squeezing Correlated Neurons for Resource-Efficient Deep Neural Networks

Algorithm-Centric Design of Reliable and Efficient Deep Learning Processing Systems

Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions

Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation

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