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A Hardware Architecture for Real-Time Video Segmentation Utilizing Memory Reduction Techniques

IEEE transactions on circuits and systems for video technology, 2009-02, Vol.19 (2), p.226-236

2009

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Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores

IEEE transactions on very large scale integration (VLSI) systems, 2006-11, Vol.14 (11), p.1286-1290

2006

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Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture

IEEE transactions on image processing, 2009-03, Vol.18 (3), p.562-572

2009

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Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements

IEEE transactions on circuits and systems. I, Regular papers, 2008-09, Vol.55 (8), p.2216-2225

2008

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Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

IEEE transactions on circuits and systems. I, Regular papers, 2008-09, Vol.55 (8), p.2411-2422

2008

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Digital implementation of a wavelet-based event detector for cardiac pacemakers

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2005-12, Vol.52 (12), p.2686-2698

2005

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Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis

IEEE transactions on circuits and systems. I, Regular papers, 2011-04, Vol.58 (4), p.827-838

2011

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Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-06, Vol.54 (6), p.537-541

2007

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An 0.8-mm ^2 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS

IEEE journal of solid-state circuits, 2013-07, Vol.48 (7), p.1680-1688

2013

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Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems

IEEE transactions on circuits and systems. I, Regular papers, 2013-03, Vol.60 (3), p.733-742

2013

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A simplified computational kernel for trellis-based decoding

IEEE communications letters, 2004-03, Vol.8 (3), p.156-158

2004

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A low logic depth complex multiplier using distributed arithmetic

IEEE journal of solid-state circuits, 2000-04, Vol.35 (4), p.656-659

2000

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Guest Editorial-ISCAS 2010 Special Issue

IEEE transactions on biomedical circuits and systems, 2011-04, Vol.5 (2), p.101-102

2011

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A 0.8 mm2 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS

2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, p.173-176

2012

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High-Level Energy Estimation in the Sub-V } Domain: Simulation and Measurement of a Cardiac Event Detector

IEEE transactions on biomedical circuits and systems, 2012-02, Vol.6 (1), p.15-27

2012

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A Receiver Architecture for Devices in Wireless Body Area Networks

IEEE journal on emerging and selected topics in circuits and systems, 2012-03, Vol.2 (1), p.82-95

2012

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Analysis of a novel low complex SNR estimation technique for OFDM systems

2011 IEEE Wireless Communications and Networking Conference, 2011, p.1646-1651

2011

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A scalable pipelined complex valued matrix inversion architecture

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.4489-4492 Vol. 5

2005

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Transmitter architecture for faster-than-Nyquist signaling systems

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.1028-1031

2009

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A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.3765-3768

2010

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Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.1696-1699

2011

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Hardware accelerator design for video segmentation with multi-modal background modelling

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1142-1145 Vol. 2

2005

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Modeling and exploration of a reconfigurable architecture for digital holographic imaging

2008 IEEE International Symposium on Circuits and Systems, 2008, p.248-251

2008

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A 2048 complex point FFT processor using a novel data scaling approach

2003 IEEE International Symposium on Circuits and Systems (ISCAS), 2003, Vol.4, p.IV-IV

2003

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An Iterative Decoder for Multicarrier Faster-Than-Nyquist Signaling Systems

2010 IEEE International Conference on Communications, 2010, p.1-5

2010

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A Hardware Architecture for Real-Time Video Segmentation Utilizing Memory Reduction Techniques

Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores

Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture

Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements

Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

Digital implementation of a wavelet-based event detector for cardiac pacemakers

Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis

Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward

An 0.8-mm ^2 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS

Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems

A simplified computational kernel for trellis-based decoding

A low logic depth complex multiplier using distributed arithmetic

Guest Editorial-ISCAS 2010 Special Issue

A 0.8 mm2 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS

High-Level Energy Estimation in the Sub-V } Domain: Simulation and Measurement of a Cardiac Event Detector

A Receiver Architecture for Devices in Wireless Body Area Networks

Analysis of a novel low complex SNR estimation technique for OFDM systems

A scalable pipelined complex valued matrix inversion architecture

Transmitter architecture for faster-than-Nyquist signaling systems

A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM

Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping

Hardware accelerator design for video segmentation with multi-modal background modelling

Modeling and exploration of a reconfigurable architecture for digital holographic imaging

A 2048 complex point FFT processor using a novel data scaling approach

An Iterative Decoder for Multicarrier Faster-Than-Nyquist Signaling Systems

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