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Capturing the sensitivity of optical network quality metrics to its network interface parameters

Concurrency and computation, 2014-10, Vol.26 (15), p.2504-2517

2014

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Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Microprocessors and microsystems, 2016-05, Vol.42, p.24-36

2016

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Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs

Journal of parallel and distributed computing, 2016-09, Vol.95, p.57-68

2016

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Shrinking L1 Instruction Caches to Improve Energy–Delay in SMT Embedded Processors

Architecture of Computing Systems – ARCS 2013, p.256-267

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A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, p.300-305

2017

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A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip

Proceedings of the 24th edition of the great lakes symposium on VLSI, 2014, p.267-272

2014

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Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2014, p.170-171

2014

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Design Automation Beyond Its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip

Photonic Interconnects for Computing Systems, 2017, p.137-169

1, 2017

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Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

IEEE transactions on very large scale integration (VLSI) systems, 2017-07, Vol.25 (7), p.2081-2094

2017

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Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2014, p.72-79

2014

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Capturing the sensitivity of optical network quality metrics to its network interface parameters

Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs

Shrinking L1 Instruction Caches to Improve Energy–Delay in SMT Embedded Processors

A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems

Design Automation Beyond Its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain

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