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A Provably Secure Strong PUF Based on LWE: Construction and Implementation

IEEE transactions on computers, 2023-02, Vol.72 (2), p.346-359

2023

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Modeling and synthesis of quality-energy optimal approximate adders

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, p.728-735

2012

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Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture

IEEE transactions on very large scale integration (VLSI) systems, 2016-04, Vol.24 (4), p.1351-1360

2016

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A general probabilistic framework for worst case timing analysis

Proceedings - ACM IEEE Design Automation Conference, 2002, p.556-561

2002

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A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks

IEEE transactions on circuits and systems. I, Regular papers, 2020-01, Vol.67 (1), p.135-144

2020

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Probabilistic strain optimization under constraint uncertainty

BMC systems biology, 2013-03, Vol.7 (1), p.29-29, Article 29

2013

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Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.712-717

2022

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Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-12, Vol.25 (12), p.2976-2988

2006

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Power-based Attacks on Spatial DNN Accelerators

ACM journal on emerging technologies in computing systems, 2022-04, Vol.18 (3), p.1-18, Article 58

2022

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Fast statistical timing analysis handling arbitrary delay correlations

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.337-342

2004

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Binary Ring-LWE hardware with power side-channel countermeasures

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, p.1253-1258

2018

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Efficient helper data reduction in SRAM PUFs via lossy compression

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, p.1453-1458

2018

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Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2020, p.273-283

2020

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A Hierarchical Classification Method for High-Accuracy Instruction Disassembly with Near-Field EM Measurements

ACM transactions on embedded computing systems, 2024-01, Vol.23 (1), p.1-21

2024

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Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols

ACM transactions on embedded computing systems, 2021-11, Vol.20 (6), p.1-22

2021

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Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems

IEEE transactions on circuits and systems for video technology, 2013-06, Vol.23 (6), p.961-974

2013

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Efficient simulation of EM side-channel attack resilience

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, p.123-130

2017

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High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks

Embedded Computer Systems: Architectures, Modeling, and Simulation, p.155-170

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NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010, p.253-258

2010

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Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-10, Vol.31 (10), p.1485-1498

2012

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Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

International Symposium on Low Power Electronics and Design (ISLPED), 2013, p.229-234

2013

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Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6

2014

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Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks

2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, p.1-2

2021

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Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-08, Vol.33 (8), p.1159-1167

2014

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SMATO: Simultaneous mask and target optimization for improving lithographic process window

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010, p.100-106

2010

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A Provably Secure Strong PUF Based on LWE: Construction and Implementation

Modeling and synthesis of quality-energy optimal approximate adders

Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture

A general probabilistic framework for worst case timing analysis

A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks

Probabilistic strain optimization under constraint uncertainty

Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM

Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation

Power-based Attacks on Spatial DNN Accelerators

Fast statistical timing analysis handling arbitrary delay correlations

Binary Ring-LWE hardware with power side-channel countermeasures

Efficient helper data reduction in SRAM PUFs via lossy compression

Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks

A Hierarchical Classification Method for High-Accuracy Instruction Disassembly with Near-Field EM Measurements

Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols

Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems

Efficient simulation of EM side-channel attack resilience

High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks

NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime

Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization

Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks

Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning

SMATO: Simultaneous mask and target optimization for improving lithographic process window

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