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Development of Materials Informatics Platform

Journal of Photopolymer Science and Technology, 2021/06/11, Vol.34(1), pp.41-47

2021

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Introduction to the Special Edition

Journal of The Japan Institute of Electronics Packaging, 2023-07, Vol.26 (4), p.325-325

Orii, Yasumitsu

2023

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Semiconductor Packaging Revolution in the Era of Chiplets

2023 International Conference on IC Design and Technology (ICICDT), 2023, p.ix-ix

Orii, Yasumitsu

2023

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Temperature Driven Current-Voltage Characteristics of Ionic Liquid Type Intelligent Connection Device

IEEE journal of the Electron Devices Society, 2022, Vol.10, p.893-897

2022

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Revitalization of Japan’s Semiconductor Industry through an All-Japan Effort

Journal of The Japan Institute of Electronics Packaging, 2021-08, Vol.24 (5), p.P5-P5

ORII, Yasumitsu

2021

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Development of Liquid Photoresist for IMS (Injection Molded Solder) with High Thermal Stability

Journal of photopolymer science and technology, 2016, Vol.29 (3), p.395

2016

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Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Journal of electronic packaging, 2012-06, Vol.134 (2)

2012

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Development of Liquid Photoresist for IMS (Injection Molded Solder) with High Thermal Stability

Journal of Photopolymer Science and Technology, 2016/06/21, Vol.29(3), pp.395-402

2016

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Solder joint reliability evaluation of chip scale package using a modified Coffin–Manson equation

Microelectronics and reliability, 2004-02, Vol.44 (2), p.269-274

2004

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Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack

2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 2011, p.125-130

2011

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Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2012, p.8-13

2012

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Combining an Integrated Sensor Array with Machine Learning for the Simultaneous Quantification of Multiple Cations in Aqueous Mixtures

Analytical chemistry (Washington), 2021-12, Vol.93 (50), p.16853-16861

2021

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Investigations of cooling solutions for three-dimensional (3D) chip stacks

2010 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2010, p.25-32

2010

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High thermal conductivity underfill for the thermal management of three-dimensional (3D) chip stacks

2014 Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2014, p.219-223

2014

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Introduction to the Special Edition

Journal of The Japan Institute of Electronics Packaging, 2014, Vol.17 (3), p.155-155

Orii, Yasumitsu

2014

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Summary and Future Visions of Materials Informatics

Journal of The Japan Institute of Electronics Packaging, 2020-03, Vol.23 (2), p.150-154

2020

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Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

Transactions of The Japan Institute of Electronics Packaging, 2011, Vol.4 (1), p.73-86

2011

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Peripheral Flip Chip Interconnection on Au Plated Pads using Solder-Capped Cu Pillar Bumps

Transactions of The Japan Institute of Electronics Packaging, 2011, Vol.4 (1), p.95-100

2011

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Wettability and Reliability for Double-Sided Assembly with Chip Connection (C2) Flip-Chip Technology

Transactions of The Japan Institute of Electronics Packaging, 2009, Vol.2 (1), p.85-90

2009

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Development of vacuum underfill technology for a 3D chip stack

Journal of micromechanics and microengineering, 2011-03, Vol.21 (3), p.035024

2011

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Core Technologies for Breaking into Cognitive Computing Era

Journal of The Japan Institute of Electronics Packaging, 2014, Vol.17 (3), p.156-162

2014

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Solder-filled Through Silicon Via with Organic Insulator

Journal of Smart Processing, 2016, Vol.5 (4), p.239-243

2016

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Solder-filled Through Silicon Via with Organic Insulator

Journal of Smart Processing, 2016, Vol.5(4), pp.239-243

2016

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Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions

29th IEEE Semiconductor Thermal Measurement and Management Symposium, 2013, p.1-6

2013

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Thermal stresses of TSV and Si chip in 3D SiP under device operation and reflow process

2014 International Conference on Electronics Packaging (ICEP), 2014, p.109-112

2014

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Development of Materials Informatics Platform

Introduction to the Special Edition

Semiconductor Packaging Revolution in the Era of Chiplets

Temperature Driven Current-Voltage Characteristics of Ionic Liquid Type Intelligent Connection Device

Revitalization of Japan’s Semiconductor Industry through an All-Japan Effort

Development of Liquid Photoresist for IMS (Injection Molded Solder) with High Thermal Stability

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Development of Liquid Photoresist for IMS (Injection Molded Solder) with High Thermal Stability

Solder joint reliability evaluation of chip scale package using a modified Coffin–Manson equation

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

Combining an Integrated Sensor Array with Machine Learning for the Simultaneous Quantification of Multiple Cations in Aqueous Mixtures

Investigations of cooling solutions for three-dimensional (3D) chip stacks

High thermal conductivity underfill for the thermal management of three-dimensional (3D) chip stacks

Introduction to the Special Edition

Summary and Future Visions of Materials Informatics

Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

Peripheral Flip Chip Interconnection on Au Plated Pads using Solder-Capped Cu Pillar Bumps

Wettability and Reliability for Double-Sided Assembly with Chip Connection (C2) Flip-Chip Technology

Development of vacuum underfill technology for a 3D chip stack

Core Technologies for Breaking into Cognitive Computing Era

Solder-filled Through Silicon Via with Organic Insulator

Solder-filled Through Silicon Via with Organic Insulator

Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions

Thermal stresses of TSV and Si chip in 3D SiP under device operation and reflow process

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