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Embedded Computer Systems: Architectures, Modeling, and Simulation: 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings

2022

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Embedded Computer Systems: Architectures, Modeling, and Simulation : 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings

2022

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JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.1323-1328

2022

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Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums

Journal of electronic testing, 2020-12, Vol.36 (6), p.703-718

2020

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Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020)

International journal of parallel programming, 2022-04, Vol.50 (2), p.187-188

2022

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Embedded Computer Systems: Architectures, Modeling, and Simulation : 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings

1st Edition 2020, 2020

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Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.3250-3262

2020

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Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1044-1057

2023

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Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1

2022

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Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1147-1160

2023

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AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction

IEEE transactions on very large scale integration (VLSI) systems, 2021-03, Vol.29 (3), p.544-557

2021

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Detecting Gas Vapor Leaks Using Uncalibrated Sensors

IEEE access, 2019, Vol.7, p.155701-155710

2019

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SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks

ACM transactions on embedded computing systems, 2021-10, Vol.20 (5s), p.1-25, Article 76

2021

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Test volume and application time reduction through scan chain concealment

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.151-155

2001

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Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

2019 IEEE 28th Asian Test Symposium (ATS), 2019, p.7-75

2019

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Piercing Logic Locking Keys through Redundancy Identification

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.540-545

2019

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The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures

Architecture of Computing Systems – ARCS 2019, p.253-266

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Just say zero: containing critical bit-error propagation in deep neural networks with anomalous feature suppression

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box

2023 IEEE 32nd Asian Test Symposium (ATS), 2023, p.1-6

2023

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Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation

2023 IEEE 41st VLSI Test Symposium (VTS), 2023, p.1-6

2023

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SNR: S queezing N umerical R ange Defuses Bit Error Vulnerability Surface in Deep Neural Networks

ACM transactions on embedded computing systems, 2021-10, Vol.20 (5s), p.1-25

2021

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Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-12, Vol.35 (12), p.2093-2103

2016

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Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-8

2021

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Special Issue on SAMOS 2022

International journal of parallel programming, 2024-04, Vol.52 (1-2), p.1-2

2024

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Test Pattern Superposition to Detect Hardware Trojans

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.25-30

2020

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Embedded Computer Systems: Architectures, Modeling, and Simulation: 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings

Embedded Computer Systems: Architectures, Modeling, and Simulation : 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings

JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption

Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums

Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020)

Embedded Computer Systems: Architectures, Modeling, and Simulation : 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings

Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection

Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis

Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation

Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction

Detecting Gas Vapor Leaks Using Uncalibrated Sensors

SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks

Test volume and application time reduction through scan chain concealment

Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

Piercing Logic Locking Keys through Redundancy Identification

The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures

Just say zero: containing critical bit-error propagation in deep neural networks with anomalous feature suppression

ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box

Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation

SNR: S queezing N umerical R ange Defuses Bit Error Vulnerability Surface in Deep Neural Networks

Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment

Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs

Special Issue on SAMOS 2022

Test Pattern Superposition to Detect Hardware Trojans

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