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Relationship between oral food intake and nausea caused by intravenous injection of iodinated contrast material

Nihon Igaku Hoshasen Gakkai zasshi. Nippon acta radiologica, 1994-05, Vol.54 (6), p.476

1994

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Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1379-1383

2006

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IEEE_Xplore

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.54-62

2006

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IEEE_Xplore

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

IEEE journal of solid-state circuits, 1995-09, Vol.30 (9), p.960-971

1995

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IEEE_Xplore

A 76-mm(2) 8-Mb chain ferroelectric memory

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1713-1720

2001

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Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's

IEEE journal of solid-state circuits, 1998-02, Vol.33 (2), p.260-267

1998

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IEEE_Xplore

885 - Predictive factors for post-prostatectomy incontinence based on urodynamic evaluation

European urology supplements : official journal of the European Association of Urology, 2019-03, Vol.18 (1), p.e1196-e1197

2019

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Predictive factors for post-prostatectomy incontinence based on urodynamic evaluation

European urology supplements : official journal of the European Association of Urology, 2019-03, Vol.18 (1), p.e1196-e1197

2019

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A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.527-530

2005

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IEEE_Xplore

Sub-0.1 mu m circuit design with substrate-over-biasing

Digest of technical papers - IEEE International Solid-State Circuits Conference, 1998

1998

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Endovascular treatment of aneurysms on the feeding arteries of intracranial arteriovenous malformations

Neuroradiology, 1999-01, Vol.41 (1), p.60-66

1999

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Open/folded bit-line arrangement for ultra-high-density DRAM's

IEEE journal of solid-state circuits, 1994-04, Vol.29 (4), p.539-542

1994

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IEEE_Xplore

An H.264/MPEG-4 audio/visual CODEC LSI with module-wise dynamic voltage/frequency scaling

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.132-589 Vol. 1

2005

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IEEE_Xplore

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.286-287

1997

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IEEE_Xplore

Standby/active mode logic for sub-1-V operating ULSI memory

IEEE journal of solid-state circuits, 1994-04, Vol.29 (4), p.441-447

1994

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IEEE_Xplore

A 76-mm2 8-Mb chain ferroelectric memory

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1713

2001

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A 76-mm/sup 2/ 8-Mb chain ferroelectric memory

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1713-1720

2001

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IEEE_Xplore

A 33-ns 64-Mb DRAM

IEEE journal of solid-state circuits, 1991-11, Vol.26 (11), p.1498-1505

1991

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IEEE_Xplore

A 76-mm super(2) 8-Mb chain ferroelectric memory

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1713-1720

2001

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Word-line architecture for highly reliable 64-Mb DRAM

IEEE journal of solid-state circuits, 1992-04, Vol.27 (4), p.603-609

1992

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IEEE_Xplore

A 76mm super(2) 8Mb chain ferroelectric memory

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2001-01

2001

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New nibbled-page architecture for high-density DRAMs

IEEE journal of solid-state circuits, 1989-08, Vol.24 (4), p.900-904

1989

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IEEE_Xplore

Open/folded bit-line arrangement for ultra-high-density DRAM's: VLSI Circuits

IEEE journal of solid-state circuits, 1994, Vol.29 (4), p.539-542

1994

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The stabilized reference-line (SRL) technique for scaled DRAMs

IEEE journal of solid-state circuits, 1990-02, Vol.25 (1), p.24-29, Article 24

1990

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IEEE_Xplore

Standby/active mode logic for sub-1-V operating ULSI memory: VLSI Circuits

IEEE journal of solid-state circuits, 1994, Vol.29 (4), p.441-447

1994

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Relationship between oral food intake and nausea caused by intravenous injection of iodinated contrast material

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

A 76-mm(2) 8-Mb chain ferroelectric memory

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's

885 - Predictive factors for post-prostatectomy incontinence based on urodynamic evaluation

Predictive factors for post-prostatectomy incontinence based on urodynamic evaluation

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI

Sub-0.1 mu m circuit design with substrate-over-biasing

Endovascular treatment of aneurysms on the feeding arteries of intracranial arteriovenous malformations

Open/folded bit-line arrangement for ultra-high-density DRAM's

An H.264/MPEG-4 audio/visual CODEC LSI with module-wise dynamic voltage/frequency scaling

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

Standby/active mode logic for sub-1-V operating ULSI memory

A 76-mm2 8-Mb chain ferroelectric memory

A 76-mm/sup 2/ 8-Mb chain ferroelectric memory

A 33-ns 64-Mb DRAM

A 76-mm super(2) 8-Mb chain ferroelectric memory

Word-line architecture for highly reliable 64-Mb DRAM

A 76mm super(2) 8Mb chain ferroelectric memory

New nibbled-page architecture for high-density DRAMs

Open/folded bit-line arrangement for ultra-high-density DRAM's: VLSI Circuits

The stabilized reference-line (SRL) technique for scaled DRAMs

Standby/active mode logic for sub-1-V operating ULSI memory: VLSI Circuits

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