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An engineering method to extract equivalent oxide thickness and its extension to channel mobility evaluation

IEEE transactions on electron devices, 2002-12, Vol.49 (12), p.2345-2348

Ootsuka, F.

2002

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Intravascular Ultrasound Predictors of Side Branch Occlusion in Bifurcation Lesions After Percutaneous Coronary Intervention

Circulation Journal, 2005, Vol.69(3), pp.325-330

2005

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The evaluation of the activation energy of interface state generation by hot-electron injection

IEEE transactions on electron devices, 1991-06, Vol.38 (6), p.1477-1483

Ootsuka, F.

1991

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Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- k FETs

IEEE transactions on electron devices, 2008-04, Vol.55 (4), p.1042-1049

2008

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Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- [Formula Omitted] FETs

IEEE transactions on electron devices, 2008-04, Vol.55 (4), p.1042-1049

2008

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Effect of Boron and Fluorine Incorporation in SiON Gate Insulator with Optimized Nitrogen Profile

Japanese Journal of Applied Physics, 2004-04, Vol.43 (4S), p.1837

2004

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Novel Silicide-Cladded Uniaxially-Strained Thin-Body SOI CMOS FETs Featuring Floating Body Modulation Induced by Hf-based Gate Dielectric

2006 IEEE international SOI Conferencee Proceedings, 2006, p.44-45

2006

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Reliability Perspective of High-k Gate Stack Assessed by Temperature Dependence of Dielectric Breakdown

2007 IEEE Symposium on VLSI Technology, 2007, p.34-35

2007

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A Novel Remote Reactive Sink Layer Technique for the Control of N and O Concentrations in Metal/High-k Gate Stacks

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers, 2006, p.164-165

2006

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Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, p.150-151

2002

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Impact of electrode-side chemical structures on electron mobility in metal/HfO/sub 2/ MISFETs with sub-1nm EOT

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.228-229

2005

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Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 2004, p.927-930

2004

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SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, 2004, p.210-211

2004

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Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications

IEEE International Electron Devices Meeting 2003, 2003, p.27.7.1-27.7.4

2003

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A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000, p.575-578

2000

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Improving Junction Uniformity and Quality with Optimized Diffusion-less Annealing

2007 International Workshop on Junction Technology, 2007, p.69-72

2007

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High-k/metal gate stack technology for advanced CMOS

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.360-363

2006

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A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platform

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.10.5.1-10.5.4

2001

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A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrciation of hp45 LOP devices

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, 2005, p.23-26

2005

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Cluster Ion Implantation for beyond 45nm node novel device applications

Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08), 2008, p.55-57

2008

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The influence of silicon nitride cap on NBTI and fermi pinning in HfO2 gate stacks

Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765), 2003, p.20-23

2003

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A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC's

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143), 1998, p.155-158

1998

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SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

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Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.19.4.1-19.4.4

2001

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A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, p.205-208

1998

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An engineering method to extract equivalent oxide thickness and its extension to channel mobility evaluation

Intravascular Ultrasound Predictors of Side Branch Occlusion in Bifurcation Lesions After Percutaneous Coronary Intervention

The evaluation of the activation energy of interface state generation by hot-electron injection

Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- k FETs

Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- [Formula Omitted] FETs

Effect of Boron and Fluorine Incorporation in SiON Gate Insulator with Optimized Nitrogen Profile

Novel Silicide-Cladded Uniaxially-Strained Thin-Body SOI CMOS FETs Featuring Floating Body Modulation Induced by Hf-based Gate Dielectric

Reliability Perspective of High-k Gate Stack Assessed by Temperature Dependence of Dielectric Breakdown

A Novel Remote Reactive Sink Layer Technique for the Control of N and O Concentrations in Metal/High-k Gate Stacks

Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

Impact of electrode-side chemical structures on electron mobility in metal/HfO/sub 2/ MISFETs with sub-1nm EOT

Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process

SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications

A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications

Improving Junction Uniformity and Quality with Optimized Diffusion-less Annealing

High-k/metal gate stack technology for advanced CMOS

A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platform

A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrciation of hp45 LOP devices

Cluster Ion Implantation for beyond 45nm node novel device applications

The influence of silicon nitride cap on NBTI and fermi pinning in HfO2 gate stacks

A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC's

SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement

A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity

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