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Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Scientific reports, 2024-01, Vol.14 (1), p.1339-1339, Article 1339

2024

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Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

IEEE transaction on neural networks and learning systems, 2023-12, Vol.34 (12), p.10999-11005

2023

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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Proceedings of the IEEE, 2016-10, Vol.104 (10), p.1844-1863

2016

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Efficient CMOS Invertible Logic Using Stochastic Computing

IEEE transactions on circuits and systems. I, Regular papers, 2019-06, Vol.66 (6), p.2263-2274

2019

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High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

IEEE transactions on very large scale integration (VLSI) systems, 2020-10, Vol.28 (10), p.2171-2181

2020

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Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

IEEE transactions on circuits and systems. I, Regular papers, 2021-01, Vol.68 (1), p.67-76

2021

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In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning

IEEE transactions on circuits and systems. I, Regular papers, 2020-05, Vol.67 (5), p.1541-1550

2020

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Gabor Filter Based on Stochastic Computation

IEEE signal processing letters, 2015-09, Vol.22 (9), p.1224-1228

2015

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High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

IEEE journal on emerging and selected topics in circuits and systems, 2023-03, Vol.13 (1), p.1-1

2023

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Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems

IEEE access, 2024, Vol.12, p.102050-102060

2024

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Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing

IEEE open journal of signal processing, 2023, Vol.4, p.452-461

2023

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Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

IEEE transactions on very large scale integration (VLSI) systems, 2015-04, Vol.23 (4), p.642-653

2015

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High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

IEEE transactions on computers, 2014-03, Vol.63 (3), p.637-649

2014

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Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation

IEEE transactions on very large scale integration (VLSI) systems, 2017-10, Vol.25 (10), p.2724-2735

2017

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Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

IEEE access, 2020, Vol.8, p.188004-188014

2020

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Sparse Random Signals for Fast Convergence on Invertible Logic

IEEE access, 2021, Vol.9, p.62890-62898

2021

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Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

IEEE open journal of circuits and systems, 2021, Vol.2, p.782-791

2021

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Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips

IEEE transactions on nanotechnology, 2016-09, Vol.15 (5), p.705-714

2016

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Networked Power-Gated MRAMs for Memory-Based Computing

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2696-2708

2018

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High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation

IEICE Transactions on Information and Systems, 2017/08/01, Vol.E100.D(8), pp.1592-1602

2017

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Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding

IEEE transactions on circuits and systems. I, Regular papers, 2011-08, Vol.58 (8), p.1933-1943

2011

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Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.482-489

2010

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A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture

IEEE journal on emerging and selected topics in circuits and systems, 2014-12, Vol.4 (4), p.460-474

2014

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Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Efficient CMOS Invertible Logic Using Stochastic Computing

High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning

Gabor Filter Based on Stochastic Computation

High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic

Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems

Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing

Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation

Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

Sparse Random Signals for Fast Convergence on Invertible Logic

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips

Networked Power-Gated MRAMs for Memory-Based Computing

High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation

Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture

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