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MTJ-based asynchronous circuits for Re-initialization free computing against power failures

Microelectronics, 2018-12, Vol.82, p.46-61

2018

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A Design Framework for Invertible Logic

2019 53rd Asilomar Conference on Signals, Systems, and Computers, 2019, p.312-316

2019

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Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning

2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), 2024, p.928-931

2024

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Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes

2012 IEEE 42nd International Symposium on Multiple-Valued Logic, 2012, p.92-97

2012

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Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013, p.254-259

2013

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Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.482-489

2010

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High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 2012, p.41-48

2012

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Architecture and implementation of an associative memory using sparse clustered networks

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.2901-2904

2012

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NoC-MRAM architecture for memory-based computing: Database-search case study

2017 15th IEEE International New Circuits and Systems Conference (NEWCAS), 2017, p.309-312

2017

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A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 2013, p.8-15

2013

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Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders

35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005, p.138-143

2005

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Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring

2011 Design, Automation & Test in Europe, 2011, p.1-6

2011

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Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links

2012 IEEE 42nd International Symposium on Multiple-Valued Logic, 2012, p.13-18

2012

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High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.157-160

2010

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Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling

IEICE transactions on electronics, 2008, Vol.E91-C (4), p.581-588

2008

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Clockless Stochastic Decoding of Low-Density Parity-Check Codes

2012 IEEE Workshop on Signal Processing Systems, 2012, p.143-148

2012

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Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links

2011 41st IEEE International Symposium on Multiple-Valued Logic, 2011, p.236-241

2011

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Biochemical characterization of cellulose-binding proteins (CBPA and CBPB) from the rumen cellulolytic bacterium Eubacterium cellulosolvens 5

Bioscience, biotechnology, and biochemistry, 2007-10, Vol.71 (10), p.2577-2580

2007

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Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control

2009 39th International Symposium on Multiple-Valued Logic, 2009, p.36-41

2009

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Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

IEICE transactions on electronics, 2006-11, Vol.E89-C (11), p.1575-1580

2006

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High-performance asynchronous intra-chip communication link based on a multiple-valued current-mode single-track scheme

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.1000-1003

2009

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3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

2007 50th Midwest Symposium on Circuits and Systems, 2007, p.217-220

2007

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High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit

38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008, p.70-75

2008

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Studies on beta 2-microglobulin in patients with collagen diseases (author's transl)

Ryumachi. [Rheumatism], 1979-06, Vol.19 (3), p.216

Onizawa, N

1979

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Multi-chip NoCs for Automotive Applications

2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012, p.105-110

2012

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MTJ-based asynchronous circuits for Re-initialization free computing against power failures

A Design Framework for Invertible Logic

Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning

Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes

Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

Architecture and implementation of an associative memory using sparse clustered networks

NoC-MRAM architecture for memory-based computing: Database-search case study

A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems

Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders

Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring

Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling

Clockless Stochastic Decoding of Low-Density Parity-Check Codes

Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links

Biochemical characterization of cellulose-binding proteins (CBPA and CBPB) from the rumen cellulolytic bacterium Eubacterium cellulosolvens 5

Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control

Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

High-performance asynchronous intra-chip communication link based on a multiple-valued current-mode single-track scheme

3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit

Studies on beta 2-microglobulin in patients with collagen diseases (author's transl)

Multi-chip NoCs for Automotive Applications

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