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Latch Susceptibility to Transient Faults and New Hardening Approach

IEEE transactions on computers, 2007-09, Vol.56 (9), p.1255-1268

2007

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Low-Cost Strategy for Bus Propagation Delay Reduction

Journal of electronic testing, 2019-04, Vol.35 (2), p.253-260

2019

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Machine learning-based predictions of directionality and charge of cosmic muons—a simulation study using the mICAL detector

Journal of instrumentation, 2019-11, Vol.14 (11), p.P11020-P11020

2019

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Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness

IEEE transactions on emerging topics in computing, 2018-10, Vol.6 (4), p.488-497

2018

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Accurate Linear Model for SET Critical Charge Estimation

IEEE transactions on very large scale integration (VLSI) systems, 2009-08, Vol.17 (8), p.1161-1166

2009

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Clock Faults Induced Min and Max Delay Violations

Journal of electronic testing, 2014-02, Vol.30 (1), p.111-123

2014

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Inverters' self-checking monitors for reliable photovoltaic systems

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.672-677

2016

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Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

Journal of electronic testing, 2013-06, Vol.29 (3), p.401-413

2013

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Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2322-2325

2011

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Cytotoxic effects induced by combination of heliantriol B2 and dequalinium against human leukemic cell lines

Phytotherapy research, 2011-04, Vol.25 (4), p.603-610

2011

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Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection

2022 IEEE 23rd Latin American Test Symposium (LATS), 2022, p.1-6

2022

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Faults affecting the control blocks of PV arrays and techniques for their concurrent detection

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012, p.199-204

2012

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Mechanisms of resistance to apoptosis in the human acute promyelocytic leukemia cell line NB4

Annals of hematology, 2015-03, Vol.94 (3), p.379-392

2015

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Multiple transient faults in logic: an issue for next generation ICs?

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005, p.352-360

2005

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Novel on-chip circuit for jitter testing in high-speed PLLs

IEEE transactions on instrumentation and measurement, 2005-10, Vol.54 (5), p.1779-1788

2005

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Effectiveness of Facilitated tucking on pain and Physiological parameters during heel lancing among neonates

International Journal of Nursing Education and Research, 2022-09, p.249-254

2022

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Low cost and high speed embedded two-rail code checker

IEEE transactions on computers, 2005-02, Vol.54 (2), p.153-164

2005

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Novel transient fault hardened static latch

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.886-892

2003

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Effectiveness of Multisensory Stimulation on Neurobehaviour among Preterm Babies

International Journal of Science and Research (IJSR), 2023-01, Vol.12 (1), p.972-974

Surendran Omana M, Arathy

2023

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Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008, p.465-473

2008

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Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009, p.127-135

2009

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New Design for Testability Approach for Clock Fault Testing

IEEE transactions on computers, 2012-04, Vol.61 (4), p.448-457

2012

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Protonic conductivity of 12-tungstophosphoric acid (TPA, H 3PW 12O 40) at elevated temperatures

Solid state ionics, 1992-12, Vol.58 (3), p.195-199

1992

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Novel Approach to Clock Fault Testing for High Performance Microprocessors

25th IEEE VLSI Test Symposium (VTS'07), 2007, p.441-446

2007

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Low cost scheme for on-line clock skew compensation

23rd IEEE VLSI Test Symposium (VTS'05), 2005, p.90-95

2005

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Latch Susceptibility to Transient Faults and New Hardening Approach

Low-Cost Strategy for Bus Propagation Delay Reduction

Machine learning-based predictions of directionality and charge of cosmic muons—a simulation study using the mICAL detector

Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness

Accurate Linear Model for SET Critical Charge Estimation

Clock Faults Induced Min and Max Delay Violations

Inverters' self-checking monitors for reliable photovoltaic systems

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

Cytotoxic effects induced by combination of heliantriol B2 and dequalinium against human leukemic cell lines

Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection

Mechanisms of resistance to apoptosis in the human acute promyelocytic leukemia cell line NB4

Multiple transient faults in logic: an issue for next generation ICs?

Novel on-chip circuit for jitter testing in high-speed PLLs

Effectiveness of Facilitated tucking on pain and Physiological parameters during heel lancing among neonates

Low cost and high speed embedded two-rail code checker

Novel transient fault hardened static latch

Effectiveness of Multisensory Stimulation on Neurobehaviour among Preterm Babies

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors

New Design for Testability Approach for Clock Fault Testing

Protonic conductivity of 12-tungstophosphoric acid (TPA, H 3PW 12O 40) at elevated temperatures

Novel Approach to Clock Fault Testing for High Performance Microprocessors

Low cost scheme for on-line clock skew compensation

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