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Instruction generation for hybrid reconfigurable systems

ACM transactions on design automation of electronic systems, 2002-10, Vol.7 (4), p.605-627

2002

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Epidemic models for phase transitions: application to a physical gel

Phase transitions, 2017-09, Vol.90 (9), p.905-913

2017

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Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

International Journal of Reconfigurable Computing, 2017-01, Vol.2017 (2017), p.1-9-008

2017

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Efficient Realization of BCD Multipliers Using FPGAs

International Journal of Reconfigurable Computing, 2017-01, Vol.2017 (2017), p.1-12-002

2017

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b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures

International Journal of Reconfigurable Computing, 2009-01, Vol.2009 (2009), p.236-247

2009

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ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

Journal of circuits, systems, and computers, 2004-02, Vol.13 (1), p.77-100

2004

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Fast floorplanning for effective prediction and construction

IEEE transactions on very large scale integration (VLSI) systems, 2001-04, Vol.9 (2), p.341-351

2001

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Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.635-640

2001

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Lazy Pipelines: Enhancing quality in approximate computing

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.1381-1386

2016

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Fault-tolerant training of neural networks in the presence of MOS transistor mismatches

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-03, Vol.48 (3), p.272-281

2001

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Edge importance identification for energy efficient graph processing

2015 IEEE International Conference on Big Data (Big Data), 2015, p.347-354

2015

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ML-Based Real-Time Control at the Edge: An Approach Using hls4ml

2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2024, p.191-191

2024

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ANNSyS: an Analog Neural Network Synthesis System

Neural networks, 1999-03, Vol.12 (2), p.325-338

1999

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Image analysis and partitioning for FPGA implementation of image restoration

2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528), 2000, p.346-355

2000

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A super-scheduler for embedded reconfigurable systems

International Conference on Computer Aided Design: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design; 04-08 Nov. 2001, 2001, p.391-394

2001

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A C to hardware/software compiler

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871), 2000, p.331-332

2000

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Instruction generation for hybrid reconfigurable systems

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.127-130

2001

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A super-scheduler for embedded reconfigurable systems

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.391-394

2001

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Temperature-aware resource allocation and binding in high-level synthesis

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.196-201

2005

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Complex event post processing for traffic accidents

2012 IEEE 13th International Symposium on Computational Intelligence and Informatics (CINTI), 2012, p.341-345

Ogrenci, A. S.

2012

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An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures

2008 International Conference on Reconfigurable Computing and FPGAs, 2008, p.97-102

2008

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A Reconfiguration-Aware Floorplacer for FPGAs

2008 International Conference on Reconfigurable Computing and FPGAs, 2008, p.109-114

2008

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Scheduling and 2D placement heuristics for partially reconfigurable systems

2009 International Conference on Field-Programmable Technology, 2009, p.223-230

2009

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FPGA implementation and analysis of image restoration

International Symposium on Field Programmable Gate Arrays: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays; 10-11 Feb. 2000, 2000, p.219-219

2000

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Instruction generation for hybrid reconfigurable systems

Epidemic models for phase transitions: application to a physical gel

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

Efficient Realization of BCD Multipliers Using FPGAs

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures

ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

Fast floorplanning for effective prediction and construction

Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Lazy Pipelines: Enhancing quality in approximate computing

Fault-tolerant training of neural networks in the presence of MOS transistor mismatches

Edge importance identification for energy efficient graph processing

ML-Based Real-Time Control at the Edge: An Approach Using hls4ml

ANNSyS: an Analog Neural Network Synthesis System

Image analysis and partitioning for FPGA implementation of image restoration

A super-scheduler for embedded reconfigurable systems

A C to hardware/software compiler

Instruction generation for hybrid reconfigurable systems

A super-scheduler for embedded reconfigurable systems

Temperature-aware resource allocation and binding in high-level synthesis

Complex event post processing for traffic accidents

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures

A Reconfiguration-Aware Floorplacer for FPGAs

Scheduling and 2D placement heuristics for partially reconfigurable systems

FPGA implementation and analysis of image restoration

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