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Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

IEEE transactions on electron devices, 2016-11, Vol.63 (11), p.4302-4308

2016

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Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

Japanese Journal of Applied Physics, 2015-04, Vol.54 (4S), p.4-1-04DC16-5

2015

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Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Japanese Journal of Applied Physics, 2014-04, Vol.53 (4S), p.4-1-04EC18-4

2014

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Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors

Japanese Journal of Applied Physics, 2013-04, Vol.52 (4), p.04CC02-04CC02-5

2013

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Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

Applied physics express, 2015-04, Vol.8 (4), p.45201

2015

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Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Journal of Low Power Electronics and Applications, 2014-04, Vol.4 (2), p.65-76

2014

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Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T38-T39

2015

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Investigation and Integration of Polycrystalline Silicon/TiN/SiON Gate Stack in Silicon on Thin Buried Oxide Complementary Metal Oxide Semiconductor Field Effect Transistors

Japanese Journal of Applied Physics, 2012-07, Vol.51 (7R), p.76504

2012

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Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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Electrical Characteristics and Crystal Quality Analysis of Thin-Body Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

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Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

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Activities of nicotinic acetylcholine receptors modulate neurotransmission and synaptic architecture

Neural regeneration research, 2014-12, Vol.9 (24), p.2128-2131

2014

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A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM

IEEE MICRO, 2015-11, Vol.35 (6), p.13-23

2015

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Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2157

2005

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Speed enhancement at V dd = 0.4 V and random τ pd variability reduction and analyisis of τ pd variability of silicon on thin buried oxide circuits

Japanese Journal of Applied Physics, 2014-04, Vol.53 (4S), p.4

2014

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Speed enhancement at Vdd = 0.4 V and random τpd variability reduction and analyisis of τpd variability of silicon on thin buried oxide circuits

Japanese Journal of Applied Physics, 2014-02, Vol.53 (4S)

2014

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Speed enhancement at V sub(dd) = 0.4V and random [tau] sub(pd) variability reduction and analyisis of [tau] sub(pd) variability of silicon on thin buried oxide circuits

Japanese Journal of Applied Physics, 2014-01, Vol.53 (4S), p.04EC07-1-04EC07-5

2014

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A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

2007 IEEE Symposium on VLSI Technology, 2007, p.78-79

2007

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Effect of a body-tie structure fabricated by partial trench isolation on the suppression of floating body effect induced soft errors in SOI SRAM investigated using nuclear probes

Nuclear instruments & methods in physics research. Section B, Beam interactions with materials and atoms, 2011-10, Vol.269 (20), p.2360-2363

2011

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(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

ECS transactions, 2015-03, Vol.66 (5), p.43-48

2015

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Difference of soft error rates in SOI SRAM induced by various high energy ion species

Nuclear instruments & methods in physics research. Section B, Beam interactions with materials and atoms, 2012-02, Vol.273, p.262-265

2012

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Improvement of Surface Morphology of Epitaxial Silicon Film for Elevated Source/Drain Ultrathin Silicon-on-Insulator Complementary-Metal-Oxide-Semiconductor Devices

Japanese Journal of Applied Physics, 2003, Vol.42 (Part 1, No. 4B), p.1971-1974

2003

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Threshold Voltage Modulation Using N+2 Implantation Into Substrate for Ni Fully Silicided Gate/High-k NMOS

IEEE electron device letters, 2008-10, Vol.29 (10), p.1163-1166

2008

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Temperature Coefficient of Threshold Voltage in High-$k$ Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4), p.04DC03-04DC03-5

2010

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Statistical analysis of minimum operation voltage (Vmin) in fully depleted silicon-on-thin-BOX (SOTB) SRAM cells

2014 Silicon Nanoelectronics Workshop (SNW), 2014, p.1-2

2014

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Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

Investigation and Integration of Polycrystalline Silicon/TiN/SiON Gate Stack in Silicon on Thin Buried Oxide Complementary Metal Oxide Semiconductor Field Effect Transistors

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Electrical Characteristics and Crystal Quality Analysis of Thin-Body Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current

Activities of nicotinic acetylcholine receptors modulate neurotransmission and synaptic architecture

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM

Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

Speed enhancement at V dd = 0.4 V and random τ pd variability reduction and analyisis of τ pd variability of silicon on thin buried oxide circuits

Speed enhancement at Vdd = 0.4 V and random τpd variability reduction and analyisis of τpd variability of silicon on thin buried oxide circuits

Speed enhancement at V sub(dd) = 0.4V and random [tau] sub(pd) variability reduction and analyisis of [tau] sub(pd) variability of silicon on thin buried oxide circuits

A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

Effect of a body-tie structure fabricated by partial trench isolation on the suppression of floating body effect induced soft errors in SOI SRAM investigated using nuclear probes

(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

Difference of soft error rates in SOI SRAM induced by various high energy ion species

Improvement of Surface Morphology of Epitaxial Silicon Film for Elevated Source/Drain Ultrathin Silicon-on-Insulator Complementary-Metal-Oxide-Semiconductor Devices

Threshold Voltage Modulation Using N+2 Implantation Into Substrate for Ni Fully Silicided Gate/High-k NMOS

Temperature Coefficient of Threshold Voltage in High-$k$ Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

Statistical analysis of minimum operation voltage (Vmin) in fully depleted silicon-on-thin-BOX (SOTB) SRAM cells

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