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An Active Approach for Charge Balancing in Functional Electrical Stimulation

IEEE transactions on biomedical circuits and systems, 2010-06, Vol.4 (3), p.162-170

2010

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Current Feedback Linearization Applied to Oscillator Based ADCs

IEEE transactions on circuits and systems. I, Regular papers, 2014-11, Vol.61 (11), p.3066-3074

2014

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A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications

Journal of micromechanics and microengineering, 2008-10, Vol.18 (10), p.104005

2008

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Highly conformable chip-in-foil implants for neural applications

Microsystems & nanoengineering, 2023-05, Vol.9 (1), p.54-54, Article 54

2023

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Low-Noise Readout Circuit for an Automotive MEMS Accelerometer

IEEE open journal of solid-state circuits, 2021, Vol.1, p.140-148

2021

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Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.28-35

Ortmanns, Maurits

2021

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Design Techniques for Energy-Efficient Analog-to-Digital Converters

IEEE open journal of solid-state circuits, 2023, Vol.3, p.145-161

2023

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Input Referred Noise of VCO-Based Comparators

IEEE transactions on circuits and systems. II, Express briefs, 2021-01, Vol.68 (1), p.82-86

2021

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Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-06, Vol.51 (6), p.1088-1099

2004

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A 0.1% THD, 1-M \Omega to 1-G \Omega Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor

IEEE journal of solid-state circuits, 2018-07, Vol.53 (7), p.1913-1923

2018

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A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2879-2891

2019

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On the Signal Filtering Property of CT Incremental Sigma-Delta ADCs

IEEE transactions on circuits and systems. II, Express briefs, 2019-11, Vol.66 (11), p.1780-1784

2019

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A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

IEEE transactions on biomedical circuits and systems, 2021-06, Vol.15 (3), p.402-411

2021

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A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing

IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.3681-3692

2020

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In Vitro Study of Artifact-Recovery Using a 32-Channel Neuromodulator Platform

IEEE transactions on circuits and systems. I, Regular papers, 2023-09, Vol.70 (9), p.3474-3483

2023

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Inner Transfer Functions in Incremental ΔΣ ADCs

IEEE transactions on circuits and systems. II, Express briefs, 2024-09, Vol.71 (9), p.4111-4115

2024

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A Dynamic Power Reduction Technique for Incremental \Delta\Sigma Modulators

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1455-1467

2019

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Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.2813-2817

2020

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A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2476-2487

2021

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Delay Error Shaping in \Delta\Sigma Modulators Using Time-Interleaved High Resolution Quantizers

IEEE transactions on circuits and systems. I, Regular papers, 2023-05, p.1-11

2023

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Feedback Receivers: Specification and State-of-the-Art Review

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW

2012 IEEE International Solid-State Circuits Conference, 2012, p.154-156

2012

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A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s

IEEE journal of solid-state circuits, 2018-05, Vol.53 (5), p.1493-1507

2018

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A Mixed-Signal TIA with Input Restoring ADC

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Delta\Sigma Modulators Employing MASH DSM DAC-Based Dual Quantization

IEEE transactions on circuits and systems. I, Regular papers, 2024-08, p.1-14

2024

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An Active Approach for Charge Balancing in Functional Electrical Stimulation

Current Feedback Linearization Applied to Oscillator Based ADCs

A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications

Highly conformable chip-in-foil implants for neural applications

Low-Noise Readout Circuit for an Automotive MEMS Accelerometer

Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Input Referred Noise of VCO-Based Comparators

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

A 0.1% THD, 1-M \Omega to 1-G \Omega Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor

A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

On the Signal Filtering Property of CT Incremental Sigma-Delta ADCs

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing

In Vitro Study of Artifact-Recovery Using a 32-Channel Neuromodulator Platform

Inner Transfer Functions in Incremental ΔΣ ADCs

A Dynamic Power Reduction Technique for Incremental \Delta\Sigma Modulators

Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF

A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

Delay Error Shaping in \Delta\Sigma Modulators Using Time-Interleaved High Resolution Quantizers

Feedback Receivers: Specification and State-of-the-Art Review

A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW

A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s

A Mixed-Signal TIA with Input Restoring ADC

Delta\Sigma Modulators Employing MASH DSM DAC-Based Dual Quantization

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