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Flexible Software-Defined Packet Processing Using Low-Area Hardware

IEEE access, 2020, Vol.8, p.98929-98945

2020

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Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach

IEICE Transactions on Information and Systems, 2018/04/01, Vol.E101.D(4), pp.1116-1125

2018

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Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures

IEICE Transactions on Information and Systems, 2018/06/01, Vol.E101.D(6), pp.1532-1540

2018

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Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator

IEICE Transactions on Information and Systems, 2017/12/01, Vol.E100.D(12), pp.2828-2836

2017

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A Scalable Body Bias Optimization Method Toward Low-Power CGRAs

IEEE MICRO, 2023-01, Vol.43 (1), p.49-57

2023

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A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL

IEEE transactions on circuits and systems. II, Express briefs, 2021-01, Vol.68 (1), p.156-160

2021

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Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.128-142

2024

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Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1578-1582

2017

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A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2021-10, Vol.29 (10), p.1800-1811

2021

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55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.102-104

2023

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Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

IEEE transactions on circuits and systems. I, Regular papers, 2018-10, Vol.65 (10), p.3241-3254

2018

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Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1254-1267

2018

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Body Bias Control for Renewable Energy Source with a High Inner Resistance

IEEE transactions on multi-scale computing systems, 2018-10, Vol.4 (4), p.605-612

2018

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Glitch-aware variable pipeline optimization for CGRAs

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2017, p.1-6

2017

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An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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Body bias grain size exploration for a coarse grained reconfigurable accelerator

2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, p.1-4

2016

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An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.207-212

2015

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A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, p.1-6

2015

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22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.21-23

2023

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Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA

2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2017, p.143-150

2017

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Leveraging asymmetric body bias control for low power LSI design

2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2017, p.1-3

2017

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SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks

2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2024, p.1-6

2024

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Body Bias Control on a CGRA based on Convex Optimization

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2022, p.1-3

2022

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A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration

2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2019, p.32-37

2019

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Design automation methodology of a critical path monitor for adaptive voltage controls

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2018, p.1-3

2018

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Flexible Software-Defined Packet Processing Using Low-Area Hardware

Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach

Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator

A Scalable Body Bias Optimization Method Toward Low-Power CGRAs

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Body Bias Control for Renewable Energy Source with a High Inner Resistance

Glitch-aware variable pipeline optimization for CGRAs

An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes

Body bias grain size exploration for a coarse grained reconfigurable accelerator

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA

Leveraging asymmetric body bias control for low power LSI design

SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks

Body Bias Control on a CGRA based on Convex Optimization

A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration

Design automation methodology of a critical path monitor for adaptive voltage controls

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