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A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1441-1447

2002

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Resonant clocking using distributed parasitic capacitance

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1520-1528

2004

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IEEE_Xplore

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

IEEE transactions on very large scale integration (VLSI) systems, 2007-11, Vol.15 (11), p.1215-1224

2007

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IEEE_Xplore

Rigorous Extraction of Process Variations for 65-nm CMOS Design

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.196-203

2009

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IEEE_Xplore

A 1.0-GHz single-issue 64-bit powerPC integer processor

IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1600-1608

1998

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IEEE_Xplore

A 32nm 0.5V-supply dual-read 6T SRAM

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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IEEE_Xplore

A 1GHz single-issue 64b powerPC processor

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2000

2000

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TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

IEEE transactions on electron devices, 2009-12, Vol.56 (12), p.3033-3040

2009

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IEEE_Xplore

A Simplified Design Model for Random Process Variability

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.12-21

2009

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IEEE_Xplore

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

IEEE transactions on very large scale integration (VLSI) systems, 2008-12, Vol.16 (12), p.1657-1665

2008

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IEEE_Xplore

Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

IEEE transactions on electron devices, 2007-09, Vol.54 (9), p.2263-2268

2007

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IEEE_Xplore

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM

IEEE transactions on circuits and systems. I, Regular papers, 2011-09, Vol.58 (9), p.2010-2016

2011

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IEEE_Xplore

Requirement-based design methods for adaptive communications links

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.93-98

2004

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IEEE_Xplore

Dynamic circuit techniques using independently controlled double-gate devices

2005 IEEE International SOI Conference Proceedings, 2005, p.74-76

2005

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IEEE_Xplore

A low-overhead virtual rail technique for SRAM leakage power reduction

2005 International Conference on Computer Design, 2005, p.574-579

2005

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IEEE_Xplore

Characterization and design for variability and reliability

2008 IEEE Custom Integrated Circuits Conference, 2008, p.341-346

2008

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IEEE_Xplore

A scheme for on-chip timing characterization

24th IEEE VLSI Test Symposium, 2006, p.6 pp.-29

2006

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IEEE_Xplore

Guest Editors' Introduction: New Dimensions in 3D Integration

IEEE design & test of computers, 2005-11, Vol.22 (6), p.496-497

2005

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IEEE_Xplore

"Timing closure by design," a high frequency microprocessor design methodology

Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000, 2000, p.712-717

2000

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IEEE_Xplore

Rapid Characterization of Threshold Voltage Fluctuation in MOS Devices

2007 IEEE International Conference on Microelectronic Test Structures, 2007, p.74-77

2007

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IEEE_Xplore

Rigorous extraction of process variations for 65nm CMOS design

ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007, p.89-92

2007

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IEEE_Xplore

Design methodology for a 1.0 GHz microprocessor

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273), 1998, p.17-23

1998

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IEEE_Xplore

Fine grained multi-threshold CMOS for enhanced leakage reduction

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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IEEE_Xplore

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength

Proceedings 2005 IEEE International SOC Conference, 2005, p.147-150

2005

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Parametric yield analysis and constrained-based supply voltage optimization

Sixth international symposium on quality electronic design (isqed'05), 2005, p.284-290

2005

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IEEE_Xplore

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A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

Resonant clocking using distributed parasitic capacitance

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

Rigorous Extraction of Process Variations for 65-nm CMOS Design

A 1.0-GHz single-issue 64-bit powerPC integer processor

A 32nm 0.5V-supply dual-read 6T SRAM

A 1GHz single-issue 64b powerPC processor

TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

A Simplified Design Model for Random Process Variability

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM

Requirement-based design methods for adaptive communications links

Dynamic circuit techniques using independently controlled double-gate devices

A low-overhead virtual rail technique for SRAM leakage power reduction

Characterization and design for variability and reliability

A scheme for on-chip timing characterization

Guest Editors' Introduction: New Dimensions in 3D Integration

"Timing closure by design," a high frequency microprocessor design methodology

Rapid Characterization of Threshold Voltage Fluctuation in MOS Devices

Rigorous extraction of process variations for 65nm CMOS design

Design methodology for a 1.0 GHz microprocessor

Fine grained multi-threshold CMOS for enhanced leakage reduction

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength

Parametric yield analysis and constrained-based supply voltage optimization

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