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Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

Active and passive electronic components, 2023-06, Vol.2023, p.1-17

2023

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FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm

International journal of performability engineering, 2021-06, Vol.17 (6), p.552

2021

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Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

International journal of electrical and computer engineering (Malacca, Malacca), 2023-08, Vol.13 (4), p.3747

2023

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A low power 10 bit SAR ADC with variable threshold technique for biomedical applications

SN applied sciences, 2019-08, Vol.1 (8), p.918, Article 918

2019

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Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

International journal of recent technology and engineering, 2019-07, Vol.8 (2), p.2406-2410

2019

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FPGA implementation of RGB image encryption and decryption using DNA cryptography

International journal of engineering & technology (Dubai), 2018-03, Vol.7 (2.8), p.397

2018

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Design of AES based Chiper and Decipher Cryptography System using Verilog HDL

Journal of physics. Conference series, 2021-02, Vol.1804 (1), p.12170

2021

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FPGA Based OTP Generation System for Data Security

International journal of recent technology and engineering, 2020-01, Vol.8 (5), p.1836-1839

2020

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Design of FPGA Based Robot Arm Controller Using Verilog HDL

Journal of physics. Conference series, 2023-04, Vol.2471 (1), p.12016

2023

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FPGA Based Health Monitoring System

International journal of recent technology and engineering, 2020-01, Vol.8 (5), p.5573-5575

2020

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FPGA Based Accident Detection and Monitoring System for Safety Traffic

International journal of recent technology and engineering, 2020-01, Vol.8 (5), p.2838-2841

2020

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Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

Turkish journal of computer and mathematics education, 2021-04, Vol.12 (3), p.5673-5683

Et. al, Barma Venkata RamaLakshmi

2021

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FPGA Based Robot Movement and Direction Controlling System

International journal of recent technology and engineering, 2020-01, Vol.8 (5), p.2638-2640

2020

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Power quality improvement for grid interconnected solar PV system using neural network control algorithm

International journal of power and energy conversion, 2018, Vol.9 (2), p.187

2018

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Power quality improvement for grid interconnected solar PV system using neural network control algorithm

International journal of power and energy conversion, 2017, Vol.9 (2), p.187

2017

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FPGA Implementation of High Speed Error Detection and Correction of Orthogonal Codes using Segmentation Method

Indian journal of science and technology, 2016-08, Vol.9 (30)

2016

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Implementation of Cryptography Algorithm with Adders and Subtractor

Indian journal of science and technology, 2017-01, Vol.10 (4)

2017

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Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA

International journal of electrical and computer engineering (Malacca, Malacca), 2016-04, Vol.6 (2), p.602

2016

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Implementation of modified Feistel block cipher for OTP generation using Verilog HDL

International journal of engineering & technology (Dubai), 2018-03, Vol.7 (2.8), p.392

2018

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Linear convolution using UT Vedic multiplier

International journal of engineering & technology (Dubai), 2018-03, Vol.7 (2.8), p.409

2018

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Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA

International journal of electrical and computer engineering (Malacca, Malacca), 2016-04, Vol.6 (2), p.602

2016

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A VLSI implementation of train collision avoidance system using Verilog HDL

International journal of engineering & technology (Dubai), 2018-03, Vol.7 (2.8), p.386

2018

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LOW POWER IMPLEMENTATION OF TRIPLE-DES BLOCK 65nm TECHNOLOGY

International journal of engineering science and technology, 2012-05, Vol.4 (5), p.2279-2279

2012

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DESIGN AND VERIFICATION OF FSM BASED TIMING GENERATOR CIRCUIT USING HDL

International journal of advances in engineering and technology, 2013-07, Vol.6 (3), p.1325-1325

2013

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Design and Testing of 16 bit Carry Save Adder using Reconfigurable LFSR

International Journal of Advanced Trends in Computer Science and Engineering, 2020-10, Vol.9 (5), p.7998-8002

2020

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Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

A low power 10 bit SAR ADC with variable threshold technique for biomedical applications

Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

FPGA implementation of RGB image encryption and decryption using DNA cryptography

Design of AES based Chiper and Decipher Cryptography System using Verilog HDL

FPGA Based OTP Generation System for Data Security

Design of FPGA Based Robot Arm Controller Using Verilog HDL

FPGA Based Health Monitoring System

FPGA Based Accident Detection and Monitoring System for Safety Traffic

Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

FPGA Based Robot Movement and Direction Controlling System

Power quality improvement for grid interconnected solar PV system using neural network control algorithm

Power quality improvement for grid interconnected solar PV system using neural network control algorithm

FPGA Implementation of High Speed Error Detection and Correction of Orthogonal Codes using Segmentation Method

Implementation of Cryptography Algorithm with Adders and Subtractor

Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA

Implementation of modified Feistel block cipher for OTP generation using Verilog HDL

Linear convolution using UT Vedic multiplier

Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA

A VLSI implementation of train collision avoidance system using Verilog HDL

LOW POWER IMPLEMENTATION OF TRIPLE-DES BLOCK 65nm TECHNOLOGY

DESIGN AND VERIFICATION OF FSM BASED TIMING GENERATOR CIRCUIT USING HDL

Design and Testing of 16 bit Carry Save Adder using Reconfigurable LFSR

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