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Implementation of scalable power and area efficient high-throughput Viterbi decoders

IEEE journal of solid-state circuits, 2002-07, Vol.37 (7), p.941-948

2002

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Design optimization of low-power high-performance DSP building blocks

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1131-1139

2004

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Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007, p.328-331

2007

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Object based refinement of motion vector fields applying probabilistic homogenization rules

IEEE transactions on consumer electronics, 2002-08, Vol.48 (3), p.694-701

2002

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Application specific instruction processor based implementation of a GNSS receiver on an FPGA

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.2, p.6 pp.

2006

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OpenMP-based parallelization on an MPCore multiprocessor platform – A performance and power analysis

Journal of systems architecture, 2008-11, Vol.54 (11), p.1019-1029

2008

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Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

Journal of systems architecture, 2007-10, Vol.53 (10), p.689-702

2007

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Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures

2009 Proceedings of ESSCIRC, 2009, p.408-411

2009

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Design flow for embedded FPGAs based on a flexible architecture template

2008 Design, Automation and Test in Europe, 2008, p.56-61

2008

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Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

Journal of systems architecture, 2007-08, Vol.53 (8), p.466-476

2007

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A parametrizable low-power high-throughput turbo-decoder

Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005, 2005, Vol.5, p.v/25-v/28 Vol. 5

2005

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Device visualization for interventional MRI using local magnetic fields: basic theory and its application to catheter visualization

IEEE transactions on medical imaging, 1998-10, Vol.17 (5), p.786-793

1998

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Error-tolerant FIR filters based on low-cost residue codes

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5210-5213 Vol. 5

2005

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A transversal equalizer with an increased adaptation speed and tracking capability

IEEE journal of solid-state circuits, 1998-03, Vol.33 (3), p.503-507

1998

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Special Issue on the 1996 ISSCC: Memory, Digital, and Signal Processing [Editorial]

IEEE journal of solid-state circuits, 1996-11, Vol.31 (11), p.1571

1996

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Object based refinement of motion vector fields applying probabilistic homogenization rules

2002 Digest of Technical Papers. International Conference on Consumer Electronics (IEEE Cat. No.02CH37300), 2002, p.340-341

2002

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Application specific eFPGAs for SoC platforms

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT), 2005, p.28

Noll, T.G.

2005

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A Fundamental Analysis of Nano-Crossbars with Non-Linear Switching Materials and its Impact on TiO2 as a Resistive Layer

2008 8th IEEE Conference on Nanotechnology, 2008, p.319-322

2008

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Optimization of device dimensions for high-performance low-power architecture blocks

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003, p.305-308

2003

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Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications

IEEE journal of solid-state circuits, 1995-03, Vol.30 (3), p.219-227

1995

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Design of a Pareto-optimization environment and its application to motion estimation

2008 IEEE 10th Workshop on Multimedia Signal Processing, 2008, p.838-843

2008

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Nano-Crossbar Arrays for Nonvolatile Resistive RAM (RRAM) Applications

2008 8th IEEE Conference on Nanotechnology, 2008, p.464-467

2008

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Limitations of electrical interconnections in electronic systems

ESSDERC '92: 22nd European Solid State Device Research conference, 1992-09, Vol.19 (1), p.561-561

Noll, T.G.

1992

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A novel systematic mapping approach for highly efficient multiplexed FIR-filter architectures

1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, 1997, Vol.1, p.651-654 vol.1

1997

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Carry-save arithmetic for high-speed digital signal processing

1990 IEEE International Symposium on Circuits and Systems (ISCAS), 1990, p.982-986 vol.2

Noll, T.G.

1990

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Implementation of scalable power and area efficient high-throughput Viterbi decoders

Design optimization of low-power high-performance DSP building blocks

Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory

Object based refinement of motion vector fields applying probabilistic homogenization rules

Application specific instruction processor based implementation of a GNSS receiver on an FPGA

OpenMP-based parallelization on an MPCore multiprocessor platform – A performance and power analysis

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures

Design flow for embedded FPGAs based on a flexible architecture template

Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

A parametrizable low-power high-throughput turbo-decoder

Device visualization for interventional MRI using local magnetic fields: basic theory and its application to catheter visualization

Error-tolerant FIR filters based on low-cost residue codes

A transversal equalizer with an increased adaptation speed and tracking capability

Special Issue on the 1996 ISSCC: Memory, Digital, and Signal Processing [Editorial]

Object based refinement of motion vector fields applying probabilistic homogenization rules

Application specific eFPGAs for SoC platforms

A Fundamental Analysis of Nano-Crossbars with Non-Linear Switching Materials and its Impact on TiO2 as a Resistive Layer

Optimization of device dimensions for high-performance low-power architecture blocks

Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications

Design of a Pareto-optimization environment and its application to motion estimation

Nano-Crossbar Arrays for Nonvolatile Resistive RAM (RRAM) Applications

Limitations of electrical interconnections in electronic systems

A novel systematic mapping approach for highly efficient multiplexed FIR-filter architectures

Carry-save arithmetic for high-speed digital signal processing

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