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A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS

IEEE transactions on electron devices, 2024-02, Vol.71 (2), p.1-6

2024

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A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

IEEE transactions on electron devices, 2021-05, Vol.68 (5), p.2265-2270

2021

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An Error Bound Particle Swarm Optimization for Analog Circuit Sizing

IEEE access, 2024-01, Vol.12, p.1-1

2024

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Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019

1st Edition 2021, 2020

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A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.2918-2922

2020

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A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications

IEEE transactions on circuits and systems. II, Express briefs, 2021-06, Vol.68 (6), p.1748-1752

2021

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Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

IEEE access, 2023, Vol.11, p.123577-123588

2023

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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

IEEE access, 2021, Vol.9, p.108119-108130

2021

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On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.3428-3432

2022

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A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), 2023, p.1-6

2023

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An Approximate Low-Power Lifting Scheme Using Reversible Logic

IEEE access, 2020, Vol.8, p.183367-183377

2020

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Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications

Integration (Amsterdam), 2021-11, Vol.81, p.268-279

2021

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Reversible Logic Implementation of Image Denoising for Grayscale Images

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.138-141

2020

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A Wideband 12 Phase Ring Oscillator for 5G Applications

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.885-888

2020

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Design and analysis of multiplier using approximate 4-2 compressor

International journal of electronics and communications, 2019-07, Vol.107, p.89-97

2019

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Design of Approximate Booth Squarer for Error-Tolerant Computing

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1230-1241

2020

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A novel tunable bandgap voltage and current reference generation circuit

Analog integrated circuits and signal processing, 2021-05, Vol.107 (2), p.331-338

2021

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A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process

IET circuits, devices & systems, 2020-05, Vol.14 (3), p.340-346

2020

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0.5 V, 254 μW Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit

Circuits, systems, and signal processing, 2021-05, Vol.40 (5), p.2114-2134

2021

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Generation of complex impedance for complex filter design using fully balanced current conveyors

Analog integrated circuits and signal processing, 2020-11, Vol.105 (2), p.203-214

2020

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Design of Approximate Dividers for Error Tolerant Applications

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018, p.496-499

2018

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A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, p.252-257

2021

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A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013, p.221-226

2013

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A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS

A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

An Error Bound Particle Swarm Optimization for Analog Circuit Sizing

Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019

A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications

A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

An Approximate Low-Power Lifting Scheme Using Reversible Logic

Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications

Reversible Logic Implementation of Image Denoising for Grayscale Images

A Wideband 12 Phase Ring Oscillator for 5G Applications

Design and analysis of multiplier using approximate 4-2 compressor

Design of Approximate Booth Squarer for Error-Tolerant Computing

A novel tunable bandgap voltage and current reference generation circuit

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process

0.5 V, 254 μW Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit

Generation of complex impedance for complex filter design using fully balanced current conveyors

Design of Approximate Dividers for Error Tolerant Applications

A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications

A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process

Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators

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