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Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier

IEEE transactions on circuits and systems. II, Express briefs, 2023-05, Vol.70 (5), p.1-1

2023

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Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2023-03, Vol.E106.A (3), p.551-559, Article 2022VLP0007

2023

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Multithread Implementation of Open Source Library Characterizer

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2024, Article 2024VLL0001

2024

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Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2022-03, Vol.E105.A (3), p.487-496, Article 2021VLP0014

2022

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Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2018-12, Vol.E101.A (12), p.2222-2230

2018

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Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2018-12, Vol.E101.A (12), p.2271-2279

2018

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Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement

IPSJ Transactions on System LSI Design Methodology, 2020, Vol.13, pp.56-64

2020

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Supplemental PDK for ASAP7 Using Synopsys Flow

IPSJ Transactions on System LSI Design Methodology, 2021, Vol.14, pp.24-26

2021

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Impact of semiconductor on diamond structure for power supply on chip applications

Japanese Journal of Applied Physics, 2014-04, Vol.53 (4S), p.4-1-04EP16-4

2014

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A Multi-Sample and Multi-Channel Technique for Electrochemical Testing and Corrosion Evaluation

Journal of testing and evaluation, 2020-03, Vol.48 (2), p.1769-1775

2020

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Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2013, Vol.E96.A (12), p.2499-2507

2013

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Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell

IPSJ Transactions on System LSI Design Methodology, 2015, Vol.8, pp.131-135

2015

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Erratum: "Impact of semiconductor on diamond structure for power supply on chip applications"

Japanese Journal of Applied Physics, 2014-04, Vol.53 (6), p.69202

2014

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Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics

2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS), 2020, p.1-4

2020

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Evaluation of SiC-MOSFET by Repetitive UIS Tests for Solid State Circuit Breaker

Materials science forum, 2020-07, Vol.1004, p.1010-1015

2020

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De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator

IEEE transactions on circuits and systems. I, Regular papers, 2024-11, Vol.71 (11), p.5187-5199

2024

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A flexible structure of standard cell and its optimization method for near-threshold voltage operation

2012 IEEE 30th International Conference on Computer Design (ICCD), 2012, p.235-240

2012

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The impact of RTN on performance fluctuation in CMOS logic circuits

2011 International Reliability Physics Symposium, 2011, p.CR.5.1-CR.5.4

2011

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A Ring Oscillator With Calibration Circuit for On-Chip Measurement of Static IR-drop

IEEE transactions on semiconductor manufacturing, 2013-08, Vol.26 (3), p.306-313

2013

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Analog circuit design methodology utilizing a structure of thin BOX FDSOI

IEICE Electronics Express, 2019, Vol.16 (5), p.20181136-20181136

2019

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NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5568-5581

2022

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Process variation aware D-Flip-Flop design using regression analysis

2018 19th International Symposium on Quality Electronic Design (ISQED), 2018, p.88-93

2018

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Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS), 2018, p.97-101

2018

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MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8

2020

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Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 2024, p.1-4

2024

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Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier

Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design

Multithread Implementation of Open Source Library Characterizer

Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells

Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis

Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution

Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement

Supplemental PDK for ASAP7 Using Synopsys Flow

Impact of semiconductor on diamond structure for power supply on chip applications

A Multi-Sample and Multi-Channel Technique for Electrochemical Testing and Corrosion Evaluation

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell

Erratum: "Impact of semiconductor on diamond structure for power supply on chip applications"

Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics

Evaluation of SiC-MOSFET by Repetitive UIS Tests for Solid State Circuit Breaker

De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator

A flexible structure of standard cell and its optimization method for near-threshold voltage operation

The impact of RTN on performance fluctuation in CMOS logic circuits

A Ring Oscillator With Calibration Circuit for On-Chip Measurement of Static IR-drop

Analog circuit design methodology utilizing a structure of thin BOX FDSOI

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map

Process variation aware D-Flip-Flop design using regression analysis

Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics

MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing

Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process

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