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A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications

IEICE transactions on electronics, 2019-04, Vol.E102.C (4), p.287-295

2019

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Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.P-CR.1-1-P-CR.1-4

2018

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A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

Japanese Journal of Applied Physics, 2013-04, Vol.52 (4), p.04CE14-04CE14-5

2013

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A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor

IEICE transactions on electronics, 2016, Vol.E99.C (8), p.901-908

2016

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Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

IEEE journal of solid-state circuits, 2023-07, Vol.58 (7), p.2098-2108

2023

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Automotive low power technology for IoT society

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T80-T81

2015

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Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1495-1499

2021

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Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation

IEICE transactions on electronics, 2012, Vol.E95.C (4), p.586-593

2012

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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

IEEE journal of solid-state circuits, 2024-08, p.1-9

2024

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A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

IEICE transactions on electronics, 2014, Vol.E97.C (4), p.332-341

2014

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Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2013, Vol.E96.A (7), p.1579-1585

2013

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A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1225-1234

2024

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Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2012-08, Vol.E95.A (8), p.1359-1365

2012

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A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

IEEE journal of solid-state circuits, 2013-11, Vol.48 (11), p.2671-2680

2013

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A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2335-2344

2018

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A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1225-1234

2024

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Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration

IEICE transactions on electronics, 2008, Vol.E91-C (9), p.1488-1500

2008

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A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.917-923

2013

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An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2347-2351

2015

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Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

Circuits and systems (Irvine, Calif.), 2012, Vol.3 (3), p.242-251

2012

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Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators

IET circuits, devices & systems, 2018-03, Vol.12 (2), p.182-188

2018

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

IEEE journal on emerging and selected topics in circuits and systems, 2016-09, Vol.6 (3), p.364-372

2016

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A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.92-101

2015

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A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications

Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

Automotive low power technology for IoT society

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration

A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

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