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Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.1189-1192

2016

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Synthesis of nonzero clock skew circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.961-976

Nieh, Y-T

2006

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Clock Period Minimization with Minimum Leakage Power

ACM transactions on design automation of electronic systems, 2015-11, Vol.21 (1), p.1-33

2015

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Minimizing peak current via opposite-phase clock tree

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.182-185

2005

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Opposite-Phase Clock Tree for Peak Current Reduction

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2007-12, Vol.E90-A (12), p.2727-2735

2007

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Opposite-phase register switching for peak current minimization

ACM transactions on design automation of electronic systems, 2009-01, Vol.14 (1), p.1-29

2009

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Clock skew scheduling with race conditions considered

ACM transactions on design automation of electronic systems, 2007-09, Vol.12 (4), p.45

2007

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Register binding for clock period minimization

Annual ACM IEEE Design Automation Conference: Proceedings of the 43rd annual conference on Design automation; 24-28 July 2006, 2006, p.439-444

2006

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Register binding for clock period minimization

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.439-444

2006

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Race-condition-aware clock skew scheduling

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.475-478

2005

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Clock period minimization with minimum delay insertion

2007 44th ACM/IEEE Design Automation Conference, 2007, p.970-975

2007

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A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains

Journal of Information Science and Engineering, 2007-11, Vol.23 (6), p.1681-1705

2007

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Low-power timing closure methodology for ultra-low voltage designs

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, p.697-704

2013

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An effective and efficient approach for layer assignment with thermal through-silicon-vias planning

2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014, p.294-297

2014

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Leakage-power-aware clock period minimization

Proceedings of the conference on Design, Automation & Test in Europe, 2014, p.1-6

2014

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Leakage-power-aware clock period minimization

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, p.1-6

2014

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Fast multi-domain clock skew scheduling for peak current reduction

Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, p.254-259

2006

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State Re-Encoding for Peak Current Minimization

2006 IEEE/ACM International Conference on Computer Aided Design, 2006, p.33-38

2006

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Clock Period Minimization of Non-Zero Clock Skew Circuits

International Conference on Computer Aided Design: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design; 09-13 Nov. 2003, 2003, p.809-809

2003

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Race-condition-aware retiming

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT), 2005, p.59-62

2005

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Minimizing peak current via opposite-phase clock tree

Proceedings. 42nd Design Automation Conference, 2005, 2005, p.182-185

2005

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Race-condition-aware clock skew scheduling

Proceedings. 42nd Design Automation Conference, 2005, 2005, p.475-478

2005

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Low-power timing closure methodology for ultra-low voltage designs

Proceedings of the International Conference on Computer-Aided Design, 2013, p.697-704

2013

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State re-encoding for peak current minimization

International Conference on Computer Aided Design: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design : San Jose, California; 05-09 Nov. 2006, 2006, p.33-38

2006

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