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Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-02, Vol.28 (2), p.285-297

2009

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Variable-length input Huffman coding for system-on-a-chip test

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-06, Vol.22 (6), p.783-796

2003

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Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-07, Vol.23 (7), p.1142-1153

2004

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Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns

IEEE transactions on very large scale integration (VLSI) systems, 2009-09, Vol.17 (9), p.1353-1357

2009

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Real-Time Lossless Compression for Silicon Debug

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-09, Vol.28 (9), p.1387-1400

2009

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Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-11, Vol.27 (11), p.2092-2097

2008

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DFT infrastructure for broadside two-pattern test of core-based SOCs

IEEE transactions on computers, 2006-04, Vol.55 (4), p.470-485

2006

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Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-08, Vol.26 (8), p.1539-1547

2007

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Modular SOC testing with reduced wrapper count

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-12, Vol.24 (12), p.1894-1908

2005

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Synchronization overhead in SOC compressed test

IEEE transactions on very large scale integration (VLSI) systems, 2005-01, Vol.13 (1), p.140-152

2005

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Modular and rapid testing of SOCs with unwrapped logic blocks

IEEE transactions on very large scale integration (VLSI) systems, 2005-11, Vol.13 (11), p.1275-1285

2005

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Wrapper design for multifrequency IP cores

IEEE transactions on very large scale integration (VLSI) systems, 2005-06, Vol.13 (6), p.678-685

2005

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An Optimal and Practical Approach to Single Constant Multiplication

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-09, Vol.30 (9), p.1373-1386

2011

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On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-12, Vol.31 (12), p.1845-1856

2012

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Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.604-611

2002

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On Using Lossy Compression for Repeatable Experiments during Silicon Debug

IEEE transactions on computers, 2011-07, Vol.60 (7), p.937-950

2011

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Multiple scan chains for power minimization during test application in sequential circuits

IEEE transactions on computers, 2002-06, Vol.51 (6), p.721-734

2002

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Multifrequency TAM design for hierarchical SOCs

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-01, Vol.25 (1), p.181-196

2006

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Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-03, Vol.29 (3), p.405-413

2010

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Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging

IEEE transactions on computers, 2012-11, Vol.61 (11), p.1563-1575

2012

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On-chip stimuli generation for post-silicon validation

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT), 2012, p.108-109

Nicolici, N.

2012

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Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Electronics letters, 2001-11, Vol.37 (24), p.1434-1436

2001

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Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison

IEEE transactions on very large scale integration (VLSI) systems, 2006-05, Vol.14 (5), p.537-548

2006

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Power profile manipulation: a new approach for reducing test application time under power constraints

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-10, Vol.21 (10), p.1217-1225

2002

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NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging

IEEE transactions on computers, 2013-03, Vol.62 (3), p.524-535

2013

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Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug

Variable-length input Huffman coding for system-on-a-chip test

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction

Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns

Real-Time Lossless Compression for Silicon Debug

Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test

DFT infrastructure for broadside two-pattern test of core-based SOCs

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Modular SOC testing with reduced wrapper count

Synchronization overhead in SOC compressed test

Modular and rapid testing of SOCs with unwrapped logic blocks

Wrapper design for multifrequency IP cores

An Optimal and Practical Approach to Single Constant Multiplication

On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging

Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression

On Using Lossy Compression for Repeatable Experiments during Silicon Debug

Multiple scan chains for power minimization during test application in sequential circuits

Multifrequency TAM design for hierarchical SOCs

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging

On-chip stimuli generation for post-silicon validation

Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison

Power profile manipulation: a new approach for reducing test application time under power constraints

NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging

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