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A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.222-229

2016

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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.150-158

2013

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A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.76-84

2011

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A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.103-110

2010

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A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.148-154

2009

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A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE journal of solid-state circuits, 2008, Vol.43 (1), p.172-179

2008

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17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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The impact of assist-circuit design for 22nm SRAM and beyond

2012 International Electron Devices Meeting, 2012, p.25.1.1-24.1.4

2012

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An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1564-1570

1999

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Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

IEEE design & test of computers, 2011-01, Vol.28 (1), p.22-31

2011

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Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM

2011 International Electron Devices Meeting, 2011, p.32.1.1-32.1.4

2011

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A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry

2012 IEEE International Solid-State Circuits Conference, 2012, p.230-232

2012

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A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.172-179

2008

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A 1.1 GHz 12 [mu]A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.172-179

2008

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A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.346-347

2010

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An 18 Mb, 12.3 GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.200-201

1999

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A 4.5 Megabit, 560MHz, 4.5 Gbyte/s High Bandwidth SRAM

Symposium 1997 on VLSI Circuits, 1997, p.15-16

1997

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A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology

The impact of assist-circuit design for 22nm SRAM and beyond

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry

A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A 1.1 GHz 12 [mu]A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation

An 18 Mb, 12.3 GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

A 4.5 Megabit, 560MHz, 4.5 Gbyte/s High Bandwidth SRAM

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