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MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply

Memories - Materials, Devices, Circuits and Systems, 2023-07, Vol.4, p.100028, Article 100028

2023

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Improved reliability single loop single feed 7T SRAM cell for biomedical applications

Memories - Materials, Devices, Circuits and Systems, 2023-07, Vol.4, p.100057, Article 100057

2023

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DOIND： a technique for leakage reduction in nanoscale domino logic circuits

Journal of semiconductors, 2016-05, Vol.37 (5), p.69-77

2016

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Improvement in Electrical Characteristics of BE-SONOS Using High-k Dielectrics in Tunneling Barrier

Transactions on Electrical and Electronic Materials, 2021, 22(3), , pp.235-242

2021

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BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

Journal of semiconductors, 2016-03, Vol.37 (3), p.42-47

2016

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Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

Microelectronics, 2024-10, Vol.152, p.106374, Article 106374

2024

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PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW

I-Manager's Journal on Circuits & Systems, 2018, Vol.6 (1), p.25

2018

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Secure SRAM Memory Design for Secret Data Protection Against Data Imprinting and Power Attack

Journal of circuits, systems, and computers, 2024-10

2024

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Proposed approximate hybrid memory architecture for handheld multimedia devices

Materials today : proceedings, 2023-04

2023

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Design of leakage current sensing technique based continues NBTI monitoring sensor using only NMOS

Materials today : proceedings, 2023, Vol.80, p.2071-2075

2023

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Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Microsystem technologies : sensors, actuators, systems integration, 2019-05, Vol.25 (5), p.1639-1652

2019

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FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)

Microsystem technologies : sensors, actuators, systems integration, 2023-10, Vol.29 (10), p.1501-1513

2023

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A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications

Journal of circuits, systems, and computers, 2021-10, Vol.30 (13)

2021

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Comparative study of decoupled read buffer SRAM memory cell for improve read noise margin

Materials today : proceedings, 2023-04

2023

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Methods for noise margin analysis of conventional 6 T and 8 T SRAM cell

Materials today : proceedings, 2023-04

2023

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Highly robust asymmetrical 9T SRAM with trimode MTCOS technique

Microsystem technologies : sensors, actuators, systems integration, 2019-05, Vol.25 (5), p.1593-1598

2019

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Novel Circuit Technique for Low Power CMOS design

World Academics Journal of Engineering Sciences, 2014, p.2008

Neema, Vaibhav

2014

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Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Journal of semiconductors, 2018-04, Vol.39 (4), p.45001

2018

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Series diode‐connected current mirror based linear and sensitive negative bias temperature instability monitoring circuit

International journal of numerical modelling, 2022-03, Vol.35 (2), p.n/a

2022

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Energy Efficient Digital Circuit Based on Self Cascoding Positive Feedback Adiabatic Logic for Low Power VLSI Design

International journal of recent technology and engineering, 2019-11, Vol.8 (2S11), p.950-954

2019

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V th Extraction Based Run Time Transistor Width (TWOS) Module for On-Chip Negative Bias Temperature Instability (NBTI) Mitigation

Sensor letters, 2019-05, Vol.17 (5), p.385-392

2019

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IMPLEMENTATION OF LOW POWER HIGH SPEED 64-BIT MEMORY UNIT USING 8T SRAM CELL AT 70 NM TECHNOLOGY

I-Manager's Journal on Electronics Engineering, 2018-06, Vol.8 (4), p.26

2018

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8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node

Procedia computer science, 2016, Vol.79, p.589-596

2016

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Investigation of Band-Gap Engineered Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory with High-k Dielectrics in Tunnel Barrier and Its Impact on Charge Retention Dynamics

Journal of nanoelectronics and optoelectronics, 2016-12, Vol.11 (6), p.663-668

2016

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A Novel Energy Efficient High-Speed 10-Transistor Full Adder Cell Based on Pass Transistor Logic

Journal of nanoelectronics and optoelectronics, 2017-05, Vol.12 (5), p.499-504

2017

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MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply

Improved reliability single loop single feed 7T SRAM cell for biomedical applications

DOIND： a technique for leakage reduction in nanoscale domino logic circuits

Improvement in Electrical Characteristics of BE-SONOS Using High-k Dielectrics in Tunneling Barrier

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW

Secure SRAM Memory Design for Secret Data Protection Against Data Imprinting and Power Attack

Proposed approximate hybrid memory architecture for handheld multimedia devices

Design of leakage current sensing technique based continues NBTI monitoring sensor using only NMOS

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)

A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications

Comparative study of decoupled read buffer SRAM memory cell for improve read noise margin

Methods for noise margin analysis of conventional 6 T and 8 T SRAM cell

Highly robust asymmetrical 9T SRAM with trimode MTCOS technique

Novel Circuit Technique for Low Power CMOS design

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Series diode‐connected current mirror based linear and sensitive negative bias temperature instability monitoring circuit

Energy Efficient Digital Circuit Based on Self Cascoding Positive Feedback Adiabatic Logic for Low Power VLSI Design

V th Extraction Based Run Time Transistor Width (TWOS) Module for On-Chip Negative Bias Temperature Instability (NBTI) Mitigation

IMPLEMENTATION OF LOW POWER HIGH SPEED 64-BIT MEMORY UNIT USING 8T SRAM CELL AT 70 NM TECHNOLOGY

8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node

Investigation of Band-Gap Engineered Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory with High-k Dielectrics in Tunnel Barrier and Its Impact on Charge Retention Dynamics

A Novel Energy Efficient High-Speed 10-Transistor Full Adder Cell Based on Pass Transistor Logic

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