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The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1392-1404

2007

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Dual-edge triggered storage elements and clocking strategy for low-power systems

IEEE transactions on very large scale integration (VLSI) systems, 2005-05, Vol.13 (5), p.577-590

2005

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A test circuit for measurement of clocked storage element characteristics

IEEE journal of solid-state circuits, 2004-08, Vol.39 (8), p.1294-1304

2004

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Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2008-11, Vol.55 (10), p.3038-3049

2008

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Methodology for Device, Circuit and Architecture Level Co-design and Optimization of Dense Wavelength Division Multiplexing Links

2023 Conference on Lasers and Electro-Optics (CLEO), 2023, p.1-2

Nedovic, N.

2023

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391 (PB-024) - Real world data: Trastuzumab w/o concurrent endocrine therapy in luminal HER2-positive metastatic breast cancer resulted in decreased overall survival

European journal of cancer (1990), 2018-04, Vol.92, p.S112-S112

2018

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Real world data: Trastuzumab w/o concurrent endocrine therapy in luminal HER2-positive metastatic breast cancer resulted in decreased overall survival

European journal of cancer (1990), 2018-04, Vol.92, p.S112

2018

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A clock skew absorbing flip-flop

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.342-497 vol.1

2003

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A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

IEEE journal of solid-state circuits, 2010-10, Vol.45 (10), p.2016-2029

2010

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Dynamic flip-flop with improved power

Proceedings of the 26th European Solid-State Circuits Conference, 2000, p.376-379

2000

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A 40-44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

IEEE journal of solid-state circuits, 2007-12, Vol.42 (12), p.2726

2007

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A 40-44 Gb/s 3x Oversampling CMOS CDR/1:16 DEMUX

IEEE journal of solid-state circuits, 2007-12, Vol.42 (12), p.2726-2735

2007

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Timing characterization of dual-edge triggered flip-flops

Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, 2001, p.538-541

2001

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A 40-44 Gb/s 3 \times Oversampling CMOS CDR/1:16 DEMUX

IEEE journal of solid-state circuits, 2007-12, Vol.42 (12), p.2726-2735

2007

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Hybrid latch flip-flop with improved power efficiency

Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843), 2000, p.211-215

2000

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Conditional techniques for low power consumption flip-flops

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001, Vol.2, p.803-806 vol.2

2001

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Hybrid latch Flip-Flop with Improved Power Efficiency

Proceedings of the 13th symposium on Integrated circuits and systems design, 2000, p.211-211

2000

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Dynamic flip-flop with improved power

Proceedings 2000 International Conference on Computer Design, 2000, p.323-326

2000

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A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium, 2009, p.1-4

2009

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Conditional pre-charge techniques for power-efficient dual-edge clocking

Proceedings of the International Symposium on Low Power Electronics and Design, 2002, p.56-59

2002

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Conditional pre-charge techniques for power-efficient dual-edge clocking

International Symposium on Low Power Electronics and Design: Proceedings of the 2002 international symposium on Low power electronics and design; 12-14 Aug. 2002, 2002, p.56-59

2002

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Comparative analysis of double-edge versus single-edge triggered clocked storage elements

2002 IEEE International Symposium on Circuits and Systems (ISCAS), 2002, Vol.5, p.V-V

2002

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Encapsulation Technologies for Active Food Ingredients and Food Processing

1. Aufl., 2009

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A low power symmetrically pulsed dual edge-triggered flip-flop

Proceedings of the 28th European Solid-State Circuits Conference, 2002, p.399-402

2002

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An overview of encapsulation technologies for food applications

Procedia food science, 2011, Vol.1, p.1806-1815

2011

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The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

Dual-edge triggered storage elements and clocking strategy for low-power systems

A test circuit for measurement of clocked storage element characteristics

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits

Methodology for Device, Circuit and Architecture Level Co-design and Optimization of Dense Wavelength Division Multiplexing Links

391 (PB-024) - Real world data: Trastuzumab w/o concurrent endocrine therapy in luminal HER2-positive metastatic breast cancer resulted in decreased overall survival

Real world data: Trastuzumab w/o concurrent endocrine therapy in luminal HER2-positive metastatic breast cancer resulted in decreased overall survival

A clock skew absorbing flip-flop

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Dynamic flip-flop with improved power

A 40-44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A 40-44 Gb/s 3x Oversampling CMOS CDR/1:16 DEMUX

Timing characterization of dual-edge triggered flip-flops

A 40-44 Gb/s 3 \times Oversampling CMOS CDR/1:16 DEMUX

Hybrid latch flip-flop with improved power efficiency

Conditional techniques for low power consumption flip-flops

Hybrid latch Flip-Flop with Improved Power Efficiency

Dynamic flip-flop with improved power

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

Conditional pre-charge techniques for power-efficient dual-edge clocking

Conditional pre-charge techniques for power-efficient dual-edge clocking

Comparative analysis of double-edge versus single-edge triggered clocked storage elements

Encapsulation Technologies for Active Food Ingredients and Food Processing

A low power symmetrically pulsed dual edge-triggered flip-flop

An overview of encapsulation technologies for food applications

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