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High-performance CMOS variability in the 65-nm regime and beyond

IBM journal of research and development, 2006-07, Vol.50 (4.5), p.433-449

2006

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Isolated Peritoneal Donor‐Related Plasmacytoma 3 Years After Liver Transplantation: A Case Report

American journal of transplantation, 2014-02, Vol.14 (2), p.472-476

2014

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Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization

IEEE transactions on semiconductor manufacturing, 2010-08, Vol.23 (3), p.345-357

2010

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Rigorous Extraction of Process Variations for 65-nm CMOS Design

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.196-203

2009

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A Simplified Design Model for Random Process Variability

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.12-21

2009

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Technique for the Rapid Characterization of Parametric Distributions

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.66-71

2009

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Power grid analysis using random walks

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-08, Vol.24 (8), p.1204-1224

2005

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Root-Finding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.22-30

2009

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A methodology for the simultaneous design of supply and signal networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-12, Vol.23 (12), p.1614-1624

2004

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A 32nm 0.5V-supply dual-read 6T SRAM

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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Layout Decomposition and Legalization for Double-Patterning Technology

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-02, Vol.32 (2), p.202-215

2013

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A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

IEEE MICRO, 2013-07, Vol.33 (4), p.46-55

2013

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Variation-aware analysis: savior of the nanometer era?

Annual ACM IEEE Design Automation Conference: Proceedings of the 43rd annual conference on Design automation; 24-28 July 2006, 2006, p.411-412

2006

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A multigrid-like technique for power grid analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-10, Vol.21 (10), p.1148-1160

2002

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Goldilocks failures: Not too soft, not too hard

2012 IEEE International Reliability Physics Symposium (IRPS), 2012, p.2F.1.1-2F.1.5

2012

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Optimal decoupling capacitor sizing and placement for standard-cell layout designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-04, Vol.22 (4), p.428-436

2003

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Early-stage power grid analysis for uncertain working modes

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-05, Vol.24 (5), p.676-682

2005

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A Methodology for Worst-Case Analysis of Integrated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1986-01, Vol.5 (1), p.104-113

1986

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Electrically-driven retargeting for nanoscale layouts

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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The care and feeding of your statistical static timer

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.138-139

2004

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FABRICS II: A Statistically Based IC Fabrication Process Simulator

IEEE transactions on computer-aided design of integrated circuits and systems, 1984-01, Vol.3 (1), p.40-46

1984

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O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction

2012 IEEE International Conference on IC Design & Technology, 2012, p.1-4

2012

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Template-mask design methodology for double patterning technology

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010, p.107-111

2010

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A chip-level electrostatic discharge simulation strategy

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.315-318

2004

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Impact of design-manufacturing interface on SoC design methodologies

IEEE design & test of computers, 2004-05, Vol.21 (3), p.183-191

2004

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High-performance CMOS variability in the 65-nm regime and beyond

Isolated Peritoneal Donor‐Related Plasmacytoma 3 Years After Liver Transplantation: A Case Report

Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization

Rigorous Extraction of Process Variations for 65-nm CMOS Design

A Simplified Design Model for Random Process Variability

Technique for the Rapid Characterization of Parametric Distributions

Power grid analysis using random walks

Root-Finding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations

A methodology for the simultaneous design of supply and signal networks

A 32nm 0.5V-supply dual-read 6T SRAM

Layout Decomposition and Legalization for Double-Patterning Technology

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Variation-aware analysis: savior of the nanometer era?

A multigrid-like technique for power grid analysis

Goldilocks failures: Not too soft, not too hard

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

Early-stage power grid analysis for uncertain working modes

A Methodology for Worst-Case Analysis of Integrated Circuits

Electrically-driven retargeting for nanoscale layouts

The care and feeding of your statistical static timer

FABRICS II: A Statistically Based IC Fabrication Process Simulator

O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction

Template-mask design methodology for double patterning technology

A chip-level electrostatic discharge simulation strategy

Impact of design-manufacturing interface on SoC design methodologies

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