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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1228-1242

2019

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A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

IEEE journal of solid-state circuits, 2016-07, Vol.51 (7), p.1630-1640

2016

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A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1375-1390

2019

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Sudden bradycardia during saline wash of the chest wall in a patient undergoing modified radical mastectomy - A case study

Indian journal of anaesthesia, 2023-09, Vol.67 (9), p.837-838

2023

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A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM

IEICE transactions on electronics, 2019-07, Vol.E102.C (7), p.595-606

2019

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A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

IEICE transactions on electronics, 2019-04, Vol.E102.C (4), p.276-286

2019

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A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

IEEE journal of solid-state circuits, 2020-09, Vol.55 (9), p.2371-2386

2020

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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2021-02, Vol.68 (2), p.603-616

2021

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A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1363-1374

2019

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ULPAC: A Miniaturized Ultralow-Power Atomic Clock

IEEE journal of solid-state circuits, 2019-11, Vol.54 (11), p.3135-3148

2019

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An AM-PM Noise Mitigation Technique in Class-C VCO

IEICE transactions on electronics, 2015-12, Vol.E98.C (12), p.1161-1170

2015

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A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI

IEICE transactions on electronics, 2017-01, Vol.E100.C (3), p.259-267

2017

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A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS

IEICE transactions on electronics, 2018-01, Vol.E101.C (2), p.126-134

2018

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High- Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

IEEE transactions on electron devices, 2015-04, Vol.62 (4), p.1269-1275

2015

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21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.344-346

2019

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General anaesthesia protocols for patients undergoing electroconvulsive therapy : retrospective analysis of 504 sessions over a five-year period at a tertiary care hospital in Oman

Sultan Qaboos University medical journal, 2017-02, Vol.17 (1), p.43-49

2017

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A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI

IEICE transactions on electronics, 2016, Vol.E99.C (6), p.632-640

2016

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Anaesthesia Management of a Patient with Hereditary Angioedema with Prophylactic Administration of C1 Esterase Inhibitor: Case Report and Literature Review

Sultan Qaboos University medical journal, 2013-08, Vol.13 (3), p.467-471

2013

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A neural network-based DPD coefficient determination for PA linearization in 5G and beyond-5G mmWave systems

IEICE Electronics Express, 2024-05, Vol.21 (10), p.20240186-20240186, Article 21.20240186

2024

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Adult sickle cell disease : a five-year experience of intensive care management in a University Hospital in Oman

Sultan Qaboos University medical journal, 2012-05, Vol.12 (2), p.177-183

2012

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A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, p.1-4

2018

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General Anaesthesia Protocols for Patients Undergoing Electroconvulsive Therapy: Retrospective Analysis of 504 Sessions over a Five-Year Period at a Tertiary Care Hospital in Oman = بروتوكلات التخدير العام للمرضى الذين يخضعون للعلاج بالجلسات الكهربائية : تحليل استرجاعي لـ 504 جلسة خلال مدة خمس سنوات في مستشفى رعاية ثالثية في عمان

Sultan Qaboos University medical journal, 2017-01, Vol.17 (1), p.43-49

2017

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0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

2019 Symposium on VLSI Circuits, 2019, p.C38-C39

2019

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A 28GHz CMOS Phased-Array Transceiver Featuring Gain Invariance Based on LO Phase Shifting Architecture with 0.1-Degree Beam-Steering Resolution for 5G New Radio

2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018, p.56-59

2018

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A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.380-383

2015

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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

Sudden bradycardia during saline wash of the chest wall in a patient undergoing modified radical mastectomy - A case study

A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS

ULPAC: A Miniaturized Ultralow-Power Atomic Clock

An AM-PM Noise Mitigation Technique in Class-C VCO

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS

High- Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

General anaesthesia protocols for patients undergoing electroconvulsive therapy : retrospective analysis of 504 sessions over a five-year period at a tertiary care hospital in Oman

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI

Anaesthesia Management of a Patient with Hereditary Angioedema with Prophylactic Administration of C1 Esterase Inhibitor: Case Report and Literature Review

A neural network-based DPD coefficient determination for PA linearization in 5G and beyond-5G mmWave systems

Adult sickle cell disease : a five-year experience of intensive care management in a University Hospital in Oman

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

A 28GHz CMOS Phased-Array Transceiver Featuring Gain Invariance Based on LO Phase Shifting Architecture with 0.1-Degree Beam-Steering Resolution for 5G New Radio

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

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