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Effect of solvent evaporation temperature on the structure of two-dimensional melamine networks on Au(111)

Japanese Journal of Applied Physics, 2016-12, Vol.55 (12), p.125001

2016

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A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

IEICE transactions on electronics, 2015-04, Vol.E98.C (4), p.333-339

2015

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Dynamical slowing down of polar nanoregion in relaxor-based ferroelctric 0.89Pb(Zn2∕3Nb1∕3)O3–0.11PbTiO3

Applied physics letters, 2006-07, Vol.89 (2)

2006

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A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

IEICE transactions on electronics, 2014, Vol.E97.C (4), p.332-341

2014

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Learning Intra-class Multimodal Distributions with Orthonormal Matrices

2024 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV), 2024, p.1859-1868

2024

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0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

IPSJ Transactions on System LSI Design Methodology, 2012, Vol.5, pp.32-43

2012

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A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

IEICE transactions on electronics, 2012-04, Vol.E95.C (4), p.523-533

2012

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Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

IEICE transactions on electronics, 2013, Vol.E96.C (4), p.528-537

2013

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7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2011, Vol.E94-A (12), p.2693-2700

2011

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0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010, p.219-224

2010

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MTTrans: Cross-domain Object Detection with Mean Teacher Transformer

Computer Vision – ECCV 2022, 2022, p.629-645

2022

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Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

Information and Media Technologies, 2012, Vol.7(2), pp.544-555

2012

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Dynamical slowing down of polar nanoregion in relaxor-based ferroelctric 0.89 Pb ( Zn 2 ∕ 3 Nb 1 ∕ 3 ) O 3 - 0.11 Pb Ti O 3

Applied physics letters, 2006-07, Vol.89 (2), p.022903-022903-3

2006

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Lossless AI: Toward Guaranteeing Consistency between Inferences Before and After Quantization via Knowledge Distillation

2021 17th International Conference on Machine Vision and Applications (MVA), 2021, p.1-5

2021

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Bit error rate estimation in SRAM considering temperature fluctuation

Thirteenth International Symposium on Quality Electronic Design (ISQED), 2012, p.516-519

2012

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Efficient Deweahter Mixture-of-Experts with Uncertainty-Aware Feature-Wise Linear Modulation

Proceedings of the ... AAAI Conference on Artificial Intelligence, 2024-03, Vol.38 (15), p.16812-16820

2024

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7T SRAM enabling low-energy simultaneous block copy

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

IEICE Electronics Express, 2012, Vol.9 (6), p.470-476

2012

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Tacrolimus and myocardial hypertrophy

Transplantation, 2000-05, Vol.69 (9), p.1960-1962

2000

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Soft Modes in SrTi18O3 Studied by Light Scattering and Dielectric Measurements

Journal of the Korean Physical Society, 2005, 46(1), , pp.93-96

2005

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Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags

International Symposium on Quality Electronic Design (ISQED), 2013, p.216-222

2013

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A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme Using Simultaneously Copyable SRAM

VLSI Design and Test for Systems Dependability, 2018, p.709-718

2018

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Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive Electronic Control Systems

VLSI Design and Test for Systems Dependability, 2018, p.539-551

2018

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Design of SRAM Resilient Against Dynamic Voltage Variations

VLSI Design and Test for Systems Dependability, 2018, p.579-591

2018

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Effect of solvent evaporation temperature on the structure of two-dimensional melamine networks on Au(111)

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Dynamical slowing down of polar nanoregion in relaxor-based ferroelctric 0.89Pb(Zn2∕3Nb1∕3)O3–0.11PbTiO3

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Learning Intra-class Multimodal Distributions with Orthonormal Matrices

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

MTTrans: Cross-domain Object Detection with Mean Teacher Transformer

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

Dynamical slowing down of polar nanoregion in relaxor-based ferroelctric 0.89 Pb ( Zn 2 ∕ 3 Nb 1 ∕ 3 ) O 3 - 0.11 Pb Ti O 3

Lossless AI: Toward Guaranteeing Consistency between Inferences Before and After Quantization via Knowledge Distillation

Bit error rate estimation in SRAM considering temperature fluctuation

Efficient Deweahter Mixture-of-Experts with Uncertainty-Aware Feature-Wise Linear Modulation

7T SRAM enabling low-energy simultaneous block copy

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Tacrolimus and myocardial hypertrophy

Soft Modes in SrTi18O3 Studied by Light Scattering and Dielectric Measurements

Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme Using Simultaneously Copyable SRAM

Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive Electronic Control Systems

Design of SRAM Resilient Against Dynamic Voltage Variations

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