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ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

International journal of e-collaboration, 2020-10, Vol.16 (4), p.59-71

2020

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ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

International journal of speech technology, 2020-06, Vol.23 (2), p.259-264

2020

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Low Power Design of 2–4 and 4–16 Line Decoders

International journal of innovative technology and exploring engineering, 2019-07, Vol.8 (9), p.1220-1224

2019

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ASIC Implementation of Fixed-Point Iterative, Parallel, and Pipeline CORDIC Algorithm

Soft Computing for Problem Solving, 2019, Vol.1048, p.341-351

2019

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Low Power, Low Area Adaptive Finite Impulse Response Filter Based on Memory Less Distributed Arithmetic

Journal of computational and theoretical nanoscience, 2018-06, Vol.15 (6), p.2003-2008

2018

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ASIC implementation of shared LUT based distributed arithmetic in FIR Filter

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017, p.1-4

2017

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ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Microelectronics, Electromagnetics and Telecommunications, 2019, Vol.521, p.385-394

2019

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Comparative Review of MAC Architectures

Soft Computing for Intelligent Systems, 2021, p.27-33

2021

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A Low Power 10 bit 50-MS/s Sample and Hold OTA Amplifier

Proceedings of the 2018 International Conference on Communication Engineering and Technology, 2018, p.33-37

2018

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Design of FINFET based DRAM cell for low power applications

Computer-Aided Developments: Electronics and Communication, 2019, p.35-43

1, 2019

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ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

Low Power Design of 2–4 and 4–16 Line Decoders

ASIC Implementation of Fixed-Point Iterative, Parallel, and Pipeline CORDIC Algorithm

Low Power, Low Area Adaptive Finite Impulse Response Filter Based on Memory Less Distributed Arithmetic

ASIC implementation of shared LUT based distributed arithmetic in FIR Filter

ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Comparative Review of MAC Architectures

A Low Power 10 bit 50-MS/s Sample and Hold OTA Amplifier

Design of FINFET based DRAM cell for low power applications

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