UB Paderborn / Katalog / Suche / in CDI

Nit1 Is a Novel Therapeutic Target for the Sensitization of Chemo- and Radiation Therapy in KRAS Mutant Lung Cancer Models

International journal of radiation oncology, biology, physics, 2014-09, Vol.90 (1), p.S805-S805

2014

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Synthesis of Timed Circuits Based on Decomposition

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-07, Vol.26 (7), p.1177-1195

2007

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Interfacing synchronous and asynchronous modules within a high-speed pipeline

IEEE transactions on very large scale integration (VLSI) systems, 2000-10, Vol.8 (5), p.573-583

2000

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An asynchronous instruction length decoder

IEEE journal of solid-state circuits, 2001-02, Vol.36 (2), p.217-228

2001

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Verification of timed circuits with failure-directed abstractions

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-03, Vol.25 (3), p.403-412

2006

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Efficient algorithms for exact two-level hazard-free logic minimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-11, Vol.21 (11), p.1269-1283

2002

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Quantifying Adenoviral Titers by Spectrophotometry

BioTechniques, 2000-03, Vol.28 (3), p.408-412

2000

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Timed state space exploration using POSETs

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-05, Vol.19 (5), p.501-520

2000

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Timed circuit verification using TEL structures

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-01, Vol.20 (1), p.129-146

2001

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MRI Brain Findings of Intravenous Iron Therapy

Neurographics (Oak Brook, Ill.), 2017-02, Vol.7 (1), p.61-63

2017

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Direct synthesis of timed circuits from free-choice STGs

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-03, Vol.21 (3), p.275-290

2002

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Asynchronous circuit design

Myers, Chris J

1st ed., 2004

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Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-03, Vol.26 (3), p.592-605

2007

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A new verification method for embedded systems

2009 IEEE International Conference on Computer Design, 2009, p.193-200

2009

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Myopathy in American miniature horses

Equine veterinary journal, 2006-05, Vol.38 (3), p.272-276

2006

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The Design of a Genetic Muller C-Element

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007, p.95-104

2007

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Hazard Checking of Timed Asynchronous Circuits Revisited

Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007, p.51-60

2007

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Synchronous interlocked pipelines

Proceedings Eighth International Symposium on Asynchronous Circuits and Systems, 2002, p.3-12

2002

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POSET timing and its application to the synthesis and verification of gate-level timed circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1999, Vol.18 (6), p.769-786

1999

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Synthesis of timed asynchronous circuits

IEEE transactions on very large scale integration (VLSI) systems, 1993-06, Vol.1 (2), p.106-119

1993

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Covering conditions and algorithms for the synthesis of speed-independent circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1998-03, Vol.17 (3), p.205-219

1998

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Architectural synthesis of timed asynchronous systems

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), 1999, p.354-363

1999

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Verification of timed circuits with failure directed abstractions

Proceedings 21st International Conference on Computer Design, 2003, p.28-35

2003

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Heterokaryotic transmission of senescence plasmid DNA in Neurospora

Current genetics, 1990-02, Vol.17 (2), p.139-145

1990

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An asynchronous implementation of the maxlist algorithm

1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, 1997, Vol.1, p.647-650 vol.1

1997

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Nit1 Is a Novel Therapeutic Target for the Sensitization of Chemo- and Radiation Therapy in KRAS Mutant Lung Cancer Models

Synthesis of Timed Circuits Based on Decomposition

Interfacing synchronous and asynchronous modules within a high-speed pipeline

An asynchronous instruction length decoder

Verification of timed circuits with failure-directed abstractions

Efficient algorithms for exact two-level hazard-free logic minimization

Quantifying Adenoviral Titers by Spectrophotometry

Timed state space exploration using POSETs

Timed circuit verification using TEL structures

MRI Brain Findings of Intravenous Iron Therapy

Direct synthesis of timed circuits from free-choice STGs

Asynchronous circuit design

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

A new verification method for embedded systems

Myopathy in American miniature horses

The Design of a Genetic Muller C-Element

Hazard Checking of Timed Asynchronous Circuits Revisited

Synchronous interlocked pipelines

POSET timing and its application to the synthesis and verification of gate-level timed circuits

Synthesis of timed asynchronous circuits

Covering conditions and algorithms for the synthesis of speed-independent circuits

Architectural synthesis of timed asynchronous systems

Verification of timed circuits with failure directed abstractions

Heterokaryotic transmission of senescence plasmid DNA in Neurospora

An asynchronous implementation of the maxlist algorithm

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